Adjust to new TargetMachine interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13956 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 1b7f547..4e825b2 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -159,7 +159,7 @@
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
- const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
const unsigned *Regs = Desc.ImplicitUses;
while (*Regs)
RegsUsed[*Regs++] = true;
@@ -184,7 +184,7 @@
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
- if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) {
+ if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the first operand