Add a blurb about the new LSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102126 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index f7d6666..82038c1 100644
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -657,7 +657,8 @@
understand assembly files. This is wired up in llvm-gcc and clang to
the <tt>-fverbose-asm</tt> option.</li>
-<li>New LSR with "full strength reduction" mode. FIXME: Description?</li>
+<li>New LSR with "full strength reduction" mode, which can reduce address
+ register pressure in loops where address generation is important.</li>
<li>A new codegen level Common Subexpression Elimination pass (MachineCSE)
is available and enabled by default. It catches redundancies exposed by