Handle the rest of pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59275 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 4bbf301..4d87efe 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -302,9 +302,10 @@
NumEmitted++; // Keep track of the # of mi's emitted
switch (MI.getDesc().TSFlags & ARMII::FormMask) {
- default:
+ default: {
assert(0 && "Unhandled instruction encoding format!");
break;
+ }
case ARMII::Pseudo:
emitPseudoInstruction(MI);
break;
@@ -509,6 +510,22 @@
switch (Opcode) {
default:
abort(); // FIXME:
+ case TargetInstrInfo::INLINEASM: {
+ const char* Value = MI.getOperand(0).getSymbolName();
+ /* We allow inline assembler nodes with empty bodies - they can
+ implicitly define registers, which is ok for JIT. */
+ assert((Value[0] == 0) && "JIT does not support inline asm!\n");
+ break;
+ }
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
+ MCE.emitLabel(MI.getOperand(0).getImm());
+ break;
+ case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::DECLARE:
+ case ARM::DWARF_LOC:
+ // Do nothing.
+ break;
case ARM::CONSTPOOL_ENTRY:
emitConstPoolInstruction(MI);
break;