commit 9e1b7ee6e84e14a314c94e7fc98f92d02266f1db
author Dan Gohman <djg@cray.com> Mon Nov 19 15:15:03 2007 +0000
committer Dan Gohman <djg@cray.com> Mon Nov 19 15:15:03 2007 +0000
tree b304a0eec3cde7be5e7e6bf61322224f093d8169
parent b642421ac2cbefb805a65c90b2c4948e711a0484

Add support in SplitVectorOp for remainder operators.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44233 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4ddcbf6..c6b4662 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -6341,7 +6341,10 @@
   case ISD::FPOW:
   case ISD::AND:
   case ISD::OR:
-  case ISD::XOR: {
+  case ISD::XOR:
+  case ISD::UREM:
+  case ISD::SREM:
+  case ISD::FREM: {
     SDOperand LL, LH, RL, RH;
     SplitVectorOp(Node->getOperand(0), LL, LH);
     SplitVectorOp(Node->getOperand(1), RL, RH);