commit 9e4816e09f50e3c4ef7368a188966944b8167ab4
author Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 13:43:18 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 13:43:18 2009 +0000
tree 1dab3dd398e45087e2d8528e74ca8e0f5a49c2ae
parent a51752cbea5d57956f177470f463baeeee33f3d7

Add shifts and reg-imm address matching

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SystemZ/SystemZInstrInfo.cpp

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index b72d0cf..cd89c04 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -61,9 +61,11 @@
 
   if (CommonRC) {
     unsigned Opc;
-    if (CommonRC == &SystemZ::GR64RegClass) {
+    if (CommonRC == &SystemZ::GR64RegClass ||
+        CommonRC == &SystemZ::ADDR64RegClass) {
       Opc = SystemZ::MOV64rr;
-    } else if (CommonRC == &SystemZ::GR32RegClass) {
+    } else if (CommonRC == &SystemZ::GR32RegClass ||
+               CommonRC == &SystemZ::ADDR32RegClass) {
       Opc = SystemZ::MOV32rr;
     } else {
       return false;
@@ -73,6 +75,20 @@
     return true;
   }
 
+  if ((SrcRC == &SystemZ::GR64RegClass &&
+       DestRC == &SystemZ::ADDR64RegClass) ||
+      (DestRC == &SystemZ::GR64RegClass &&
+       SrcRC == &SystemZ::ADDR64RegClass)) {
+    BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
+    return true;
+  } else if ((SrcRC == &SystemZ::GR32RegClass &&
+              DestRC == &SystemZ::ADDR32RegClass) ||
+             (DestRC == &SystemZ::GR32RegClass &&
+              SrcRC == &SystemZ::ADDR32RegClass)) {
+    BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
+    return true;
+  }
+
   return false;
 }