Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 7acd03e..ba2a193 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -88,7 +88,7 @@
assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
"Extract subreg and Dst must be of same register class");
- MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC);
+ MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
}
@@ -157,7 +157,7 @@
} else {
TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
}
- MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
+ MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
@@ -184,7 +184,7 @@
assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
"Insert superreg and Dst must be of same register class");
- MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0);
+ MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
@@ -206,7 +206,7 @@
} else {
TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
}
- MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
+ MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index fec9e2e..ffec6ca 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -135,7 +135,7 @@
// into the phi node destination.
//
const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
- RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
+ RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
// Update live variable information if there is any...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
@@ -200,7 +200,7 @@
MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
// Insert the copy.
- RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC);
+ RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC);
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index b775122..a6e32b2 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -365,7 +365,7 @@
} else {
// Create the reg, emit the copy.
VRBase = RegMap->createVirtualRegister(TRC);
- MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
+ MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
}
if (InstanceNo > 0)
@@ -769,7 +769,7 @@
TRC = getPhysicalRegisterRegClass(MRI,
Node->getOperand(2).getValueType(),
InReg);
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
+ MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
}
break;
}
@@ -854,9 +854,11 @@
if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
E = MF.livein_end(); LI != E; ++LI)
- if (LI->second)
+ if (LI->second) {
+ const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
- LI->first, RegMap->getRegClass(LI->second));
+ LI->first, RC, RC);
+ }
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
index 286ef1f..4f0a74b 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
@@ -684,9 +684,11 @@
if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
E = MF.livein_end(); LI != E; ++LI)
- if (LI->second)
+ if (LI->second) {
+ const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
- LI->first, RegMap->getRegClass(LI->second));
+ LI->first, RC, RC);
+ }
}
DenseMap<SDOperand, unsigned> VRBaseMap;
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 372b1b3..9c32388 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -192,7 +192,7 @@
InstructionRearranged:
const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
- MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
+ MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
MachineBasicBlock::iterator prevMi = prior(mi);
DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 8a1432e..c6ac4b2 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -926,7 +926,7 @@
const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
MF.setPhysRegUsed(DesignatedReg);
ReusedOperands.markClobbered(DesignatedReg);
- MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
+ MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
MachineInstr *CopyMI = prior(MII);
UpdateKills(*CopyMI, RegKills, KillOps);
@@ -1009,8 +1009,9 @@
if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
DOUT << "Promoted Load To Copy: " << MI;
if (DestReg != InReg) {
- MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
- MF.getSSARegMap()->getRegClass(VirtReg));
+ const TargetRegisterClass *RC =
+ MF.getSSARegMap()->getRegClass(VirtReg);
+ MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
// Revisit the copy so we make sure to notice the effects of the
// operation on the destreg (either needing to RA it if it's
// virtual or needing to clobber any values if it's physical).