Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22366 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 3225963..aeb15a0 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -419,7 +419,7 @@
                               DAG.getConstant(8, MVT::i64));
   return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1, 
                      DAG.getConstant(VarArgsOffset, MVT::i64), SA2, 
-                     DAG.getSrcValue(VAListV, 8), MVT::i32);
+                     DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
 }
 
 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
@@ -457,7 +457,8 @@
                                     DAG.getConstant(8, MVT::i64));
   SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, 
                                  Result.getValue(1), NewOffset, 
-                                 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
+                                 Tmp, DAG.getSrcValue(VAListV, 8),
+                                 DAG.getValueType(MVT::i32));
   Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
 
   return std::make_pair(Result, Update);
@@ -478,7 +479,8 @@
   SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, 
                              DAG.getConstant(8, MVT::i64));
   return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
-                     Val, NPD, DAG.getSrcValue(DestV, 8), MVT::i32);
+                     Val, NPD, DAG.getSrcValue(DestV, 8),
+                     DAG.getValueType(MVT::i32));
 }
 
 namespace {
@@ -2283,7 +2285,7 @@
         case MVT::f32: Opc = Alpha::STS; break;
         }
       } else { //ISD::TRUNCSTORE
-        switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+        switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
         default: assert(0 && "unknown Type in store");
         case MVT::i1: //FIXME: DAG does not promote this load
         case MVT::i8: Opc = Alpha::STB; break;