diff --git a/lib/CodeGen/MachinePassRegistry.cpp b/lib/CodeGen/MachinePassRegistry.cpp
index a5f4408..c440992 100644
--- a/lib/CodeGen/MachinePassRegistry.cpp
+++ b/lib/CodeGen/MachinePassRegistry.cpp
@@ -1,4 +1,4 @@
-//===-- MachineInstr.cpp --------------------------------------------------===//
+//===-- CodeGen/MachineInstr.cpp ------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,9 +6,13 @@
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+//
+// This file contains the machine function pass registry for register allocators
+// and instruction schedulers.
+//
+//===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MachinePassRegistry.h"
-#include <iostream>
 
 using namespace llvm;
 
diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp
index 04f390a..a896f83 100644
--- a/lib/CodeGen/Passes.cpp
+++ b/lib/CodeGen/Passes.cpp
@@ -27,13 +27,13 @@
 }
 
 FunctionPass *llvm::createRegisterAllocator() {
-  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getCache();
+  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
   
   if (!Ctor) {
     Ctor = RegisterRegAlloc::FindCtor(RegAlloc);
     assert(Ctor && "No register allocator found");
     if (!Ctor) Ctor = RegisterRegAlloc::FirstCtor();
-    RegisterRegAlloc::setCache(Ctor);
+    RegisterRegAlloc::setDefault(Ctor);
   }
   
   assert(Ctor && "No register allocator found");
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 3d24973..8b82197 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -21,6 +21,7 @@
 #define DEBUG_TYPE "sched"
 #include "llvm/CodeGen/MachinePassRegistry.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
@@ -519,9 +520,10 @@
 /// createTDListDAGScheduler - This creates a top-down list scheduler with a
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
-ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG *DAG,
+ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
+                                            SelectionDAG *DAG,
                                             MachineBasicBlock *BB) {
   return new ScheduleDAGList(*DAG, BB, DAG->getTarget(),
                              new LatencyPriorityQueue(),
-                             new HazardRecognizer());
+                             IS->CreateTargetHazardRecognizer());
 }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index d0e9afc..6e7ef2e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -886,13 +886,15 @@
 //                         Public Constructor Functions
 //===----------------------------------------------------------------------===//
 
-llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
+                                                    SelectionDAG *DAG,
                                                     MachineBasicBlock *BB) {
   return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
                                new BURegReductionPriorityQueue<bu_ls_rr_sort>());
 }
 
-llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
+                                                    SelectionDAG *DAG,
                                                     MachineBasicBlock *BB) {
   return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
                                new TDRegReductionPriorityQueue<td_ls_rr_sort>());
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
index 88587ce..2b8a754 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
@@ -1120,21 +1120,24 @@
 
 /// createSimpleDAGScheduler - This creates a simple two pass instruction
 /// scheduler using instruction itinerary.
-llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAGISel *IS,
+                                                  SelectionDAG *DAG,
                                                   MachineBasicBlock *BB) {
   return new ScheduleDAGSimple(false, false, *DAG, BB, DAG->getTarget());
 }
 
 /// createNoItinsDAGScheduler - This creates a simple two pass instruction
 /// scheduler without using instruction itinerary.
-llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAGISel *IS,
+                                                   SelectionDAG *DAG,
                                                    MachineBasicBlock *BB) {
   return new ScheduleDAGSimple(false, true, *DAG, BB, DAG->getTarget());
 }
 
 /// createBFS_DAGScheduler - This creates a simple breadth first instruction
 /// scheduler.
-llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAGISel *IS,
+                                                SelectionDAG *DAG,
                                                 MachineBasicBlock *BB) {
   return new ScheduleDAGSimple(true, false, *DAG, BB,  DAG->getTarget());
 }
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index dd3959b..84daabb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -67,7 +67,7 @@
               cl::init("default"),
               cl::desc("Instruction schedulers available:"));
 
-  RegisterScheduler
+  static RegisterScheduler
   defaultListDAGScheduler("default", "  Best scheduler for the target", NULL);
 } // namespace
 
@@ -3611,7 +3611,7 @@
   if (ViewSchedDAGs) DAG.viewGraph();
 
   static RegisterScheduler::FunctionPassCtor Ctor =
-                                                  RegisterScheduler::getCache();
+                                                RegisterScheduler::getDefault();
   
   if (!Ctor) {
     if (std::string("default") == std::string(ISHeuristic)) {
@@ -3629,16 +3629,21 @@
       Ctor = RegisterScheduler::FindCtor(ISHeuristic);
     }
     
-     RegisterScheduler::setCache(Ctor);
+     RegisterScheduler::setDefault(Ctor);
   }
   
   assert(Ctor && "No instruction scheduler found");
-  ScheduleDAG *SL = Ctor(&DAG, BB);
+  ScheduleDAG *SL = Ctor(this, &DAG, BB);
   BB = SL->Run();
   delete SL;
 }
 
 
+HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
+  return new HazardRecognizer();
+}
+
+
 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
 /// by tblgen.  Others should not call it.
 void SelectionDAGISel::