add basic encoding support for immediates and registers, allowing us
to encode all of these instructions correctly (for example):
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x01,0x00,0x08]
stwu r1, -64(r1) ; encoding: [0x94,0x21,0xff,0xc0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119118 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
index 889fe0f..fd98f4d 100644
--- a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
@@ -13,6 +13,7 @@
#define DEBUG_TYPE "mccodeemitter"
#include "PPC.h"
+#include "PPCRegisterInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCInst.h"
#include "llvm/ADT/Statistic.h"
@@ -91,6 +92,12 @@
unsigned PPCMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
+ if (MO.isReg())
+ return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
+
+ if (MO.isImm())
+ return MO.getImm();
+
// FIXME.
return 0;
}