commit a05dca4f9e051fad19fe9b5f6cce2715c1e5d505
author Dale Johannesen <dalej@apple.com> Wed Feb 04 23:02:30 2009 +0000
committer Dale Johannesen <dalej@apple.com> Wed Feb 04 23:02:30 2009 +0000
tree a3cd3f34942f47cebb56e1d3f8cd111fd62535cb
parent 4d452de1506344bf1d28bb4a8c4ddb78c51a28c8

Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelLowering.cpp

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index a6c4d8b..16e2deb 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -652,6 +652,7 @@
 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
   SDValue Copy;
   SDValue Chain = Op.getOperand(0);
+  DebugLoc dl = Op.getDebugLoc();
   switch(Op.getNumOperands()) {
   default:
     assert(0 && "Do not know how to return this many arguments!");
@@ -672,13 +673,14 @@
       return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, 
                          Op.getValue(1), Sign);
     }
-    Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue());
+    Copy = DAG.getCopyToReg(Chain, dl, ARM::R0, Op, SDValue());
     if (DAG.getMachineFunction().getRegInfo().liveout_empty())
       DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
     break;
   case 5:
-    Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue());
-    Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
+    Copy = DAG.getCopyToReg(Chain, dl, ARM::R1, Op.getOperand(3), SDValue());
+    Copy = DAG.getCopyToReg(Copy, dl, ARM::R0, Op.getOperand(1), 
+                            Copy.getValue(1));
     // If we haven't noted the R0+R1 are live out, do so now.
     if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
       DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
@@ -686,10 +688,13 @@
     }
     break;
   case 9:  // i128 -> 4 regs
-    Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue());
-    Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1));
-    Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1));
-    Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1));
+    Copy = DAG.getCopyToReg(Chain, dl, ARM::R3, Op.getOperand(7), SDValue());
+    Copy = DAG.getCopyToReg(Copy , dl, ARM::R2, Op.getOperand(5),
+                            Copy.getValue(1));
+    Copy = DAG.getCopyToReg(Copy , dl, ARM::R1, Op.getOperand(3),
+                            Copy.getValue(1));
+    Copy = DAG.getCopyToReg(Copy , dl, ARM::R0, Op.getOperand(1),
+                            Copy.getValue(1));
     // If we haven't noted the R0+R1 are live out, do so now.
     if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
       DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);