Tabs -> spaces, and remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82355 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index be04740..197b3b6 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -162,7 +162,7 @@
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
llvm_unreachable(0);
- return 0;
+ return 0;
}
/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
@@ -225,7 +225,7 @@
bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
assert(Emitted && "Unable to issue a live-in copy instruction!\n");
(void) Emitted;
-
+
CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
if (Coalesced) {
if (&*InsertPos == UseMI) ++InsertPos;
@@ -379,13 +379,13 @@
// as a tail call, cease emitting nodes for this block.
for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I) {
if (MDDbgKind) {
- // Update DebugLoc if debug information is attached with this
+ // Update DebugLoc if debug information is attached with this
// instruction.
- if (MDNode *Dbg =
- dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, I))) {
- DILocation DILoc(Dbg);
- DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
- SDL->setCurDebugLoc(Loc);
+ if (MDNode *Dbg =
+ dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, I))) {
+ DILocation DILoc(Dbg);
+ DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
+ SDL->setCurDebugLoc(Loc);
}
}
if (!isa<TerminatorInst>(I))
@@ -407,7 +407,7 @@
SDL->visit(*LLVMBB->getTerminator());
}
}
-
+
// Make sure the root of the DAG is up-to-date.
CurDAG->setRoot(SDL->getControlRoot());
@@ -419,44 +419,44 @@
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
SmallPtrSet<SDNode*, 128> VisitedNodes;
SmallVector<SDNode*, 128> Worklist;
-
+
Worklist.push_back(CurDAG->getRoot().getNode());
-
+
APInt Mask;
APInt KnownZero;
APInt KnownOne;
-
+
while (!Worklist.empty()) {
SDNode *N = Worklist.back();
Worklist.pop_back();
-
+
// If we've already seen this node, ignore it.
if (!VisitedNodes.insert(N))
continue;
-
+
// Otherwise, add all chain operands to the worklist.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
if (N->getOperand(i).getValueType() == MVT::Other)
Worklist.push_back(N->getOperand(i).getNode());
-
+
// If this is a CopyToReg with a vreg dest, process it.
if (N->getOpcode() != ISD::CopyToReg)
continue;
-
+
unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
if (!TargetRegisterInfo::isVirtualRegister(DestReg))
continue;
-
+
// Ignore non-scalar or non-integer values.
SDValue Src = N->getOperand(2);
EVT SrcVT = Src.getValueType();
if (!SrcVT.isInteger() || SrcVT.isVector())
continue;
-
+
unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
-
+
// Only install this information if it tells us something.
if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
DestReg -= TargetRegisterInfo::FirstVirtualRegister;
@@ -494,10 +494,10 @@
} else {
CurDAG->Combine(Unrestricted, *AA, OptLevel);
}
-
+
DEBUG(errs() << "Optimized lowered selection DAG:\n");
DEBUG(CurDAG->dump());
-
+
// Second step, hack on the DAG until it only uses operations and types that
// the target supports.
if (!DisableLegalizeTypes) {
@@ -561,7 +561,7 @@
DEBUG(CurDAG->dump());
}
}
-
+
if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
if (TimePassesIsEnabled) {
@@ -570,10 +570,10 @@
} else {
CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
}
-
+
DEBUG(errs() << "Legalized selection DAG:\n");
DEBUG(CurDAG->dump());
-
+
if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
// Run the DAG combiner in post-legalize mode.
@@ -583,12 +583,12 @@
} else {
CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
}
-
+
DEBUG(errs() << "Optimized legalized selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
-
+
if (OptLevel != CodeGenOpt::None)
ComputeLiveOutVRegInfo();
@@ -617,7 +617,7 @@
if (ViewSUnitDAGs) Scheduler->viewGraph();
- // Emit machine code to BB. This can change 'BB' to the last block being
+ // Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Creation", GroupName);
@@ -636,7 +636,7 @@
DEBUG(errs() << "Selected machine code:\n");
DEBUG(BB->dump());
-}
+}
void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
MachineFunction &MF,
@@ -740,17 +740,17 @@
FastIS->startNewBlock(BB);
// Do FastISel on as many instructions as possible.
for (; BI != End; ++BI) {
- if (MDDbgKind) {
- // Update DebugLoc if debug information is attached with this
- // instruction.
- if (MDNode *Dbg =
- dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, BI))) {
- DILocation DILoc(Dbg);
- DebugLoc Loc = ExtractDebugLocation(DILoc,
- MF.getDebugLocInfo());
- FastIS->setCurDebugLoc(Loc);
- }
- }
+ if (MDDbgKind) {
+ // Update DebugLoc if debug information is attached with this
+ // instruction.
+ if (MDNode *Dbg =
+ dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, BI))) {
+ DILocation DILoc(Dbg);
+ DebugLoc Loc = ExtractDebugLocation(DILoc,
+ MF.getDebugLocInfo());
+ FastIS->setCurDebugLoc(Loc);
+ }
+ }
// Just before the terminator instruction, insert instructions to
// feed PHI nodes in successor blocks.
@@ -760,7 +760,7 @@
errs() << "FastISel miss: ";
BI->dump();
}
- assert(!EnableFastISelAbort &&
+ assert(!EnableFastISelAbort &&
"FastISel didn't handle a PHI in a successor");
break;
}
@@ -838,7 +838,7 @@
errs() << "Node " << i << " : ("
<< SDL->PHINodesToUpdate[i].first
<< ", " << SDL->PHINodesToUpdate[i].second << ")\n");
-
+
// Next, now that we know what the last MBB the LLVM BB expanded is, update
// PHI nodes in successors.
if (SDL->SwitchCases.empty() &&
@@ -867,7 +867,7 @@
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
- }
+ }
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
// Set the current basic block to the mbb we wish to insert the code into
@@ -882,8 +882,8 @@
SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
SDL->BitTestCases[i].Reg,
SDL->BitTestCases[i].Cases[j]);
-
-
+
+
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
@@ -936,7 +936,7 @@
CodeGenAndEmitDAG();
SDL->clear();
}
-
+
// Set the current basic block to the mbb we wish to insert the code into
BB = SDL->JTCases[i].second.MBB;
SDL->setCurrentBasicBlock(BB);
@@ -945,7 +945,7 @@
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
-
+
// Update PHI Nodes
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
@@ -968,7 +968,7 @@
}
}
SDL->JTCases.clear();
-
+
// If the switch block involved a branch to one of the actual successors, we
// need to update PHI nodes in that block.
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
@@ -981,19 +981,19 @@
PHI->addOperand(MachineOperand::CreateMBB(BB));
}
}
-
+
// If we generated any switch lowering information, build and codegen any
// additional DAGs necessary.
for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
// Set the current basic block to the mbb we wish to insert the code into
MachineBasicBlock *ThisBB = BB = SDL->SwitchCases[i].ThisBB;
SDL->setCurrentBasicBlock(BB);
-
+
// Emit the code
SDL->visitSwitchCase(SDL->SwitchCases[i]);
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
-
+
// Handle any PHI nodes in successors of this chunk, as if we were coming
// from the original BB before switch expansion. Note that PHI nodes can
// occur multiple times in PHINodesToUpdate. We have to be very careful to
@@ -1020,11 +1020,11 @@
}
}
}
-
+
// Don't process RHS if same block as LHS.
if (BB == SDL->SwitchCases[i].FalseBB)
SDL->SwitchCases[i].FalseBB = 0;
-
+
// If we haven't handled the RHS, do so now. Otherwise, we're done.
SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
SDL->SwitchCases[i].FalseBB = 0;
@@ -1044,12 +1044,12 @@
///
ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
-
+
if (!Ctor) {
Ctor = ISHeuristic;
RegisterScheduler::setDefault(Ctor);
}
-
+
return Ctor(this, OptLevel);
}
@@ -1066,25 +1066,25 @@
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
-
+
// If the actual mask exactly matches, success!
if (ActualMask == DesiredMask)
return true;
-
+
// If the actual AND mask is allowing unallowed bits, this doesn't match.
if (ActualMask.intersects(~DesiredMask))
return false;
-
+
// Otherwise, the DAG Combiner may have proven that the value coming in is
// either already zero or is not demanded. Check for known zero input bits.
APInt NeededMask = DesiredMask & ~ActualMask;
if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
return true;
-
+
// TODO: check to see if missing bits are just not demanded.
// Otherwise, this pattern doesn't match.
@@ -1095,32 +1095,32 @@
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
-
+
// If the actual mask exactly matches, success!
if (ActualMask == DesiredMask)
return true;
-
+
// If the actual AND mask is allowing unallowed bits, this doesn't match.
if (ActualMask.intersects(~DesiredMask))
return false;
-
+
// Otherwise, the DAG Combiner may have proven that the value coming in is
// either already zero or is not demanded. Check for known zero input bits.
APInt NeededMask = DesiredMask & ~ActualMask;
-
+
APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
-
+
// If all the missing bits in the or are already known to be set, match!
if ((NeededMask & KnownOne) == NeededMask)
return true;
-
+
// TODO: check to see if missing bits are just not demanded.
-
+
// Otherwise, this pattern doesn't match.
return false;
}
@@ -1139,7 +1139,7 @@
unsigned i = 2, e = InOps.size();
if (InOps[e-1].getValueType() == MVT::Flag)
--e; // Don't process a flag operand if it is here.
-
+
while (i != e) {
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
if ((Flags & 7) != 4 /*MEM*/) {
@@ -1156,7 +1156,7 @@
llvm_report_error("Could not match memory address. Inline asm"
" failure!");
}
-
+
// Add this to the output node.
EVT IntPtrTy = TLI.getPointerTy();
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
@@ -1165,7 +1165,7 @@
i += 2;
}
}
-
+
// Add the flag input back if present.
if (e != InOps.size())
Ops.push_back(InOps.back());