diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h
index ef48453..362b354 100644
--- a/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -118,11 +118,6 @@
       return I->second;
     }
 
-    bool hasInterval(unsigned reg) const {
-      Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
-      return I != r2iMap_.end();
-    }
-
     /// getMBBStartIdx - Return the base index of the first instruction in the
     /// specified MachineBasicBlock.
     unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
@@ -194,7 +189,6 @@
     /// copies that cannot yet be coallesced into the "TryAgain" list.
     void CopyCoallesceInMBB(MachineBasicBlock *MBB,
                             std::vector<CopyRec> &TryAgain);
-
     /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
     /// which are the src/dst of the copy instruction CopyMI.  This returns true
     /// if the copy was successfully coallesced away, or if it is never possible
@@ -239,9 +233,6 @@
                                    LiveInterval &interval,
                                    unsigned SrcReg);
 
-    /// handleLiveInRegister - Create interval for a livein register.
-    void handleLiveInRegister(MachineBasicBlock* mbb, LiveInterval &interval);
-
     /// Return true if the two specified registers belong to different
     /// register classes.  The registers may be either phys or virt regs.
     bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
@@ -250,16 +241,11 @@
     bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
                               MachineInstr *CopyMI);
 
-    /// hasRegisterUse - Returns true if there is any use of the specific
-    /// reg between indexes Start and End.
-    bool hasRegisterUse(unsigned Reg, unsigned Start, unsigned End);
+    bool overlapsAliases(const LiveInterval *lhs,
+                         const LiveInterval *rhs) const;
 
     static LiveInterval createInterval(unsigned Reg);
 
-    void removeInterval(unsigned Reg) {
-      r2iMap_.erase(Reg);
-    }
-
     LiveInterval &getOrCreateInterval(unsigned reg) {
       Reg2IntervalMap::iterator I = r2iMap_.find(reg);
       if (I == r2iMap_.end())
diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h
index 786a1fd..6e7e23d 100644
--- a/include/llvm/CodeGen/LiveVariables.h
+++ b/include/llvm/CodeGen/LiveVariables.h
@@ -36,7 +36,6 @@
 namespace llvm {
 
 class MRegisterInfo;
-class BitVector;
 
 class LiveVariables : public MachineFunctionPass {
 public:
@@ -109,11 +108,11 @@
   ///
   std::vector<VarInfo> VirtRegInfo;
 
-  /// ReservedRegisters - This vector keeps track of which registers
-  /// are reserved register which are not allocatable by the target machine.
-  /// We can not track liveness for values that are in this set.
+  /// AllocatablePhysicalRegisters - This vector keeps track of which registers
+  /// are actually register allocatable by the target machine.  We can not track
+  /// liveness for values that are not in this set.
   ///
-  BitVector ReservedRegisters;
+  BitVector AllocatablePhysicalRegisters;
 
 private:   // Intermediate data structures
   const MRegisterInfo *RegInfo;
diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h
index 661430c..142f8d8 100644
--- a/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/include/llvm/CodeGen/MachineBasicBlock.h
@@ -138,18 +138,11 @@
   /// is an error to add the same register to the same set more than once.
   void addLiveIn(unsigned Reg)  { LiveIns.push_back(Reg); }
 
-  /// removeLiveIn - Remove the specified register from the live in set.
-  ///
-  void removeLiveIn(unsigned Reg);
-
   // Iteration support for live in sets.  These sets are kept in sorted
   // order by their register number.
-  typedef std::vector<unsigned>::iterator       livein_iterator;
-  typedef std::vector<unsigned>::const_iterator const_livein_iterator;
-  livein_iterator       livein_begin()       { return LiveIns.begin(); }
-  const_livein_iterator livein_begin() const { return LiveIns.begin(); }
-  livein_iterator       livein_end()         { return LiveIns.end(); }
-  const_livein_iterator livein_end()   const { return LiveIns.end(); }
+  typedef std::vector<unsigned>::const_iterator livein_iterator;
+  livein_iterator livein_begin() const { return LiveIns.begin(); }
+  livein_iterator livein_end()   const { return LiveIns.end(); }
   bool            livein_empty() const { return LiveIns.empty(); }
 
   // Code Layout methods.
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 9cefe7b..ad2ccdf 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -393,10 +393,6 @@
   /// the specific register or NULL if it is not found.
   MachineOperand *findRegisterUseOperand(unsigned Reg);
   
-  /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
-  /// the specific register or NULL if it is not found.
-  MachineOperand *findRegisterDefOperand(unsigned Reg);
-  
   /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
   ///
   void copyKillDeadInfo(const MachineInstr *MI);
diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index da111e6..6d53d51 100644
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -284,17 +284,6 @@
     return false;
   }
 
-  /// regsOverlap - Returns true if the two registers are equal or alias
-  /// each other. The registers may be virtual register.
-  bool regsOverlap(unsigned regA, unsigned regB) const {
-    if (regA == regB)
-      return true;
-
-    if (isVirtualRegister(regA) || isVirtualRegister(regB))
-      return false;
-    return areAliases(regA, regB);
-  }
-
   /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee saved registers on this target. The register should be in the
   /// order of desired callee-save stack frame offset. The first register is
@@ -306,12 +295,6 @@
   /// length of this list match the getCalleeSaveRegs() list.
   virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
 
-  /// getReservedRegs - Returns a bitset indexed by physical register number
-  /// indicating if a register is a special register that has particular uses and
-  /// should be considered unavailable at all times, e.g. SP, RA. This is used by
-  /// register scavenger to determine what registers are free.
-  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
-
   //===--------------------------------------------------------------------===//
   // Register Class Information
   //
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 70a791b..57a73d2 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -98,6 +98,28 @@
     // Set the MBB2IdxMap entry for this MBB.
     MBB2IdxMap[MBB->getNumber()] = MIIndex;
 
+    // If this BB has any live ins, insert a dummy instruction at the
+    // beginning of the function that we will pretend "defines" the values. This
+    // is to make the interval analysis simpler by providing a number.
+    if (MBB->livein_begin() != MBB->livein_end()) {
+      unsigned FirstLiveIn = *MBB->livein_begin();
+
+      // Find a reg class that contains this live in.
+      const TargetRegisterClass *RC = 0;
+      for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
+             RCE = mri_->regclass_end(); RCI != RCE; ++RCI)
+        if ((*RCI)->contains(FirstLiveIn)) {
+          RC = *RCI;
+          break;
+        }
+
+      MachineInstr *OldFirstMI = MBB->begin();
+      mri_->copyRegToReg(*MBB, MBB->begin(),
+                         FirstLiveIn, FirstLiveIn, RC);
+      assert(OldFirstMI != MBB->begin() &&
+             "copyRetToReg didn't insert anything!");
+    }
+    
     for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
          I != E; ++I) {
       bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
@@ -139,16 +161,7 @@
       if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
           (RegRep = rep(srcReg)) == rep(dstReg)) {
         // remove from def list
-        LiveInterval &RegInt = getOrCreateInterval(RegRep);
-        MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
-        // If def of this move instruction is dead, remove its live range from
-        // the dstination register's live interval.
-        if (MO->isDead()) {
-          unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
-          RegInt.removeRange(*RegInt.FindLiveRangeContaining(MoveIdx));
-          if (RegInt.empty())
-            removeInterval(RegRep);
-        }
+        getOrCreateInterval(RegRep);
         RemoveMachineInstrFromMaps(mii);
         mii = mbbi->erase(mii);
         ++numPeep;
@@ -172,6 +185,7 @@
     }
   }
 
+  
   for (iterator I = begin(), E = end(); I != E; ++I) {
     LiveInterval &LI = I->second;
     if (MRegisterInfo::isVirtualRegister(LI.reg)) {
@@ -656,43 +670,6 @@
   }
 }
 
-void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
-                                         LiveInterval &interval) {
-  DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
-
-  // Look for kills, if it reaches a def before it's killed, then it shouldn't
-  // be considered a livein.
-  MachineBasicBlock::iterator mi = MBB->begin();
-  unsigned baseIndex = 0;
-  unsigned start = 0;
-  unsigned end = start;
-  while (mi != MBB->end()) {
-    if (lv_->KillsRegister(mi, interval.reg)) {
-      DOUT << " killed";
-      end = getUseIndex(baseIndex) + 1;
-      goto exit;
-    } else if (lv_->ModifiesRegister(mi, interval.reg)) {
-      // Another instruction redefines the register before it is ever read.
-      // Then the register is essentially dead at the instruction that defines
-      // it. Hence its interval is:
-      // [defSlot(def), defSlot(def)+1)
-      DOUT << " dead";
-      end = getDefIndex(start) + 1;
-      goto exit;
-    }
-
-    baseIndex += InstrSlots::NUM;
-    ++mi;
-  }
-
-exit:
-  assert(start < end && "did not find end of interval?");
-
-  LiveRange LR(start, end, interval.getNextValue(~0U, 0));
-  interval.addRange(LR);
-  DOUT << " +" << LR << '\n';
-}
-
 /// computeIntervals - computes the live intervals for virtual
 /// registers. for some ordering of the machine instructions [1,N] a
 /// live interval is an interval [i, j) where 1 <= i <= j < N for
@@ -711,13 +688,17 @@
     MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
 
     if (MBB->livein_begin() != MBB->livein_end()) {
-      // Create intervals for live-ins to this BB first.
-      for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
+      // Process live-ins to this BB first.
+      for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
              LE = MBB->livein_end(); LI != LE; ++LI) {
-        handleLiveInRegister(MBB, getOrCreateInterval(*LI));
+        handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
+                                  getOrCreateInterval(*LI), 0);
         for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
-          handleLiveInRegister(MBB, getOrCreateInterval(*AS));
+          handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
+                                    getOrCreateInterval(*AS), 0);
       }
+      ++MI;
+      MIIndex += InstrSlots::NUM;
     }
     
     for (; MI != miEnd; ++MI) {
@@ -834,6 +815,7 @@
   return true;
 }
 
+
 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
 /// which are the src/dst of the copy instruction CopyMI.  This returns true
 /// if the copy was successfully coallesced away, or if it is never possible
@@ -843,93 +825,54 @@
 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
                              unsigned SrcReg, unsigned DstReg) {
   DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
-
+  
   // Get representative registers.
-  unsigned repSrcReg = rep(SrcReg);
-  unsigned repDstReg = rep(DstReg);
+  SrcReg = rep(SrcReg);
+  DstReg = rep(DstReg);
   
   // If they are already joined we continue.
-  if (repSrcReg == repDstReg) {
+  if (SrcReg == DstReg) {
     DOUT << "\tCopy already coallesced.\n";
     return true;  // Not coallescable.
   }
   
   // If they are both physical registers, we cannot join them.
-  if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
-      MRegisterInfo::isPhysicalRegister(repDstReg)) {
+  if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
+      MRegisterInfo::isPhysicalRegister(DstReg)) {
     DOUT << "\tCan not coallesce physregs.\n";
     return true;  // Not coallescable.
   }
   
   // We only join virtual registers with allocatable physical registers.
-  if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
-      !allocatableRegs_[repSrcReg]) {
+  if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
     DOUT << "\tSrc reg is unallocatable physreg.\n";
     return true;  // Not coallescable.
   }
-  if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
-      !allocatableRegs_[repDstReg]) {
+  if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
     DOUT << "\tDst reg is unallocatable physreg.\n";
     return true;  // Not coallescable.
   }
   
   // If they are not of the same register class, we cannot join them.
-  if (differingRegisterClasses(repSrcReg, repDstReg)) {
+  if (differingRegisterClasses(SrcReg, DstReg)) {
     DOUT << "\tSrc/Dest are different register classes.\n";
     return true;  // Not coallescable.
   }
   
-  LiveInterval &SrcInt = getInterval(repSrcReg);
-  LiveInterval &DestInt = getInterval(repDstReg);
-  assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
+  LiveInterval &SrcInt = getInterval(SrcReg);
+  LiveInterval &DestInt = getInterval(DstReg);
+  assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
          "Register mapping is horribly broken!");
   
   DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
   DOUT << " and "; DestInt.print(DOUT, mri_);
   DOUT << ": ";
-
-  // Check if it is necessary to propagate "isDead" property before intervals
-  // are joined.
-  MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
-  bool isDead = mopd->isDead();
-  unsigned SrcStart = 0;
-  unsigned SrcEnd = 0;
-  if (isDead) {
-    unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
-    LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1);
-    SrcStart = SrcLR->start;
-    SrcEnd   = SrcLR->end;
-    if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd))
-      isDead = false;
-  }
-
+    
   // Okay, attempt to join these two intervals.  On failure, this returns false.
   // Otherwise, if one of the intervals being joined is a physreg, this method
   // always canonicalizes DestInt to be it.  The output "SrcInt" will not have
   // been modified, so we can use this information below to update aliases.
-  if (JoinIntervals(DestInt, SrcInt)) {
-    if (isDead) {
-      // Result of the copy is dead. Propagate this property.
-      if (SrcStart == 0) {
-        // Live-in to the function but dead. Remove it from MBB live-in set.
-        // JoinIntervals may end up swapping the two intervals.
-        LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt;
-        LiveInInt.removeRange(SrcStart, SrcEnd);
-        MachineBasicBlock *MBB = CopyMI->getParent();
-        MBB->removeLiveIn(SrcReg);
-      } else {
-        MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
-        if (SrcMI) {
-          // FIXME: SrcMI == NULL means the register is livein to a non-entry
-          // MBB. Remove the range from its live interval?
-          MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
-          if (mops)
-            // FIXME: mops == NULL means SrcMI defines a subregister?
-            mops->setIsDead();
-        }
-      }
-    }
-  } else {
+  if (!JoinIntervals(DestInt, SrcInt)) {
     // Coallescing failed.
     
     // If we can eliminate the copy without merging the live ranges, do so now.
@@ -941,17 +884,17 @@
     return false;
   }
 
-  bool Swapped = repSrcReg == DestInt.reg;
+  bool Swapped = SrcReg == DestInt.reg;
   if (Swapped)
-    std::swap(repSrcReg, repDstReg);
-  assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
+    std::swap(SrcReg, DstReg);
+  assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
          "LiveInterval::join didn't work right!");
                                
   // If we're about to merge live ranges into a physical register live range,
   // we have to update any aliased register's live ranges to indicate that they
   // have clobbered values for this range.
-  if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
-    for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
+  if (MRegisterInfo::isPhysicalRegister(DstReg)) {
+    for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
       getInterval(*AS).MergeInClobberRanges(SrcInt);
   }
 
@@ -961,8 +904,8 @@
   // If the intervals were swapped by Join, swap them back so that the register
   // mapping (in the r2i map) is correct.
   if (Swapped) SrcInt.swap(DestInt);
-  removeInterval(repSrcReg);
-  r2rMap_[repSrcReg] = repDstReg;
+  r2iMap_.erase(SrcReg);
+  r2rMap_[SrcReg] = DstReg;
 
   // Finally, delete the copy instruction.
   RemoveMachineInstrFromMaps(CopyMI);
@@ -1446,29 +1389,6 @@
     return !RegClass->contains(RegB);
 }
 
-/// hasRegisterUse - Returns true if there is any use of the specific
-/// reg between indexes Start and End.
-bool
-LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) {
-  for (unsigned Index = Start+InstrSlots::NUM; Index != End;
-       Index += InstrSlots::NUM) {
-    // Skip deleted instructions
-    while (Index != End && !getInstructionFromIndex(Index))
-      Index += InstrSlots::NUM;
-    if (Index >= End) break;
-
-    MachineInstr *MI = getInstructionFromIndex(Index);
-    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg() && MO.isUse() && MO.getReg() &&
-          mri_->regsOverlap(rep(MO.getReg()), Reg))
-        return true;
-    }
-  }
-
-  return false;
-}
-
 LiveInterval LiveIntervals::createInterval(unsigned reg) {
   float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
                        HUGE_VALF : 0.0F;
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index a976626..c0da92c 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -71,11 +71,31 @@
   return VirtRegInfo[RegIdx];
 }
 
+/// registerOverlap - Returns true if register 1 is equal to register 2
+/// or if register 1 is equal to any of alias of register 2.
+static bool registerOverlap(unsigned Reg1, unsigned Reg2,
+                             const MRegisterInfo *RegInfo) {
+  bool isVirt1 = MRegisterInfo::isVirtualRegister(Reg1);
+  bool isVirt2 = MRegisterInfo::isVirtualRegister(Reg2);
+  if (isVirt1 != isVirt2)
+    return false;
+  if (Reg1 == Reg2)
+    return true;
+  else if (isVirt1)
+    return false;
+  for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg2);
+       unsigned Alias = *AliasSet; ++AliasSet) {
+    if (Reg1 == Alias)
+      return true;
+  }
+  return false;
+}
+
 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (MO.isReg() && MO.isKill()) {
-      if (RegInfo->regsOverlap(Reg, MO.getReg()))
+      if (registerOverlap(Reg, MO.getReg(), RegInfo))
         return true;
     }
   }
@@ -86,7 +106,7 @@
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (MO.isReg() && MO.isDead())
-      if (RegInfo->regsOverlap(Reg, MO.getReg()))
+      if (registerOverlap(Reg, MO.getReg(), RegInfo))
         return true;
   }
   return false;
@@ -96,7 +116,7 @@
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (MO.isReg() && MO.isDef()) {
-      if (RegInfo->regsOverlap(Reg, MO.getReg()))
+      if (registerOverlap(Reg, MO.getReg(), RegInfo))
         return true;
     }
   }
@@ -220,7 +240,7 @@
   RegInfo = MF.getTarget().getRegisterInfo();
   assert(RegInfo && "Target doesn't have register information?");
 
-  ReservedRegisters = RegInfo->getReservedRegs(MF);
+  AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
 
   // PhysRegInfo - Keep track of which instruction was the last use of a
   // physical register.  This is a purely local property, because all physical
@@ -247,8 +267,8 @@
          E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
     MachineBasicBlock *MBB = *DFI;
 
-    // Mark live-in registers as live-in.
-    for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
+  // Mark live-in registers as live-in.
+    for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
            EE = MBB->livein_end(); II != EE; ++II) {
       assert(MRegisterInfo::isPhysicalRegister(*II) &&
              "Cannot have a live-in virtual register!");
@@ -275,7 +295,7 @@
           if (MRegisterInfo::isVirtualRegister(MO.getReg())){
             HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
           } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
-                     !ReservedRegisters[MO.getReg()]) {
+                     AllocatablePhysicalRegisters[MO.getReg()]) {
             HandlePhysRegUse(MO.getReg(), MI);
           }
         }
@@ -293,7 +313,7 @@
             // Defaults to dead
             VRInfo.Kills.push_back(MI);
           } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
-                     !ReservedRegisters[MO.getReg()]) {
+                     AllocatablePhysicalRegisters[MO.getReg()]) {
             HandlePhysRegDef(MO.getReg(), MI);
           }
         }
diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index bef2502..d67159d 100644
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -118,7 +118,7 @@
   const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo();  
   if (livein_begin() != livein_end()) {
     OS << "Live Ins:";
-    for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
+    for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
       OutputReg(OS, *I, MRI);
     OS << "\n";
   }
@@ -144,12 +144,6 @@
   }
 }
 
-void MachineBasicBlock::removeLiveIn(unsigned Reg) {
-  livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
-  assert(I != livein_end() && "Not a live in!");
-  LiveIns.erase(I);
-}
-
 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
   MachineFunction::BasicBlockListType &BBList =getParent()->getBasicBlockList();
   getParent()->getBasicBlockList().splice(NewAfter, BBList, this);
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 01a3e3e..a393133 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -180,17 +180,6 @@
   return NULL;
 }
   
-/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
-/// the specific register or NULL if it is not found.
-MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
-  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = getOperand(i);
-    if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
-      return &MO;
-  }
-  return NULL;
-}
-  
 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
 ///
 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 3a1bfc2..bd44e81 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -292,9 +292,8 @@
   }
 
   // A brute force way of adding live-ins to every BB.
-  MachineFunction::iterator MBB = mf_->begin();
-  ++MBB; // Skip entry MBB.
-  for (MachineFunction::iterator E = mf_->end(); MBB != E; ++MBB) {
+  for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
+       MBB != E; ++MBB) {
     unsigned StartIdx = li_->getMBBStartIdx(MBB->getNumber());
     for (IntervalPtrs::iterator i = fixed_.begin(), e = fixed_.end();
          i != e; ++i)
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 41f5e46..a96be56 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -28,7 +28,6 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
-#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <algorithm>
@@ -298,20 +297,6 @@
   return CalleeSavedRegClasses;
 }
 
-BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(ARM::SP);
-  if (STI.isTargetDarwin() || hasFP(MF))
-    Reserved.set(FramePtr);
-  // Some targets reserve R9.
-  if (STI.isR9Reserved())
-    Reserved.set(ARM::R9);
-  // At PEI time, if LR is used, it will be spilled upon entry.
-  if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR))
-    Reserved.set(ARM::LR);
-  return Reserved;
-}
-
 /// hasFP - Return true if the specified function should have a dedicated frame
 /// pointer register.  This is true if the function has variable sized allocas
 /// or if frame pointer elimination is disabled.
diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h
index d5c8021..e46da07 100644
--- a/lib/Target/ARM/ARMRegisterInfo.h
+++ b/lib/Target/ARM/ARMRegisterInfo.h
@@ -67,8 +67,6 @@
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-
   bool hasFP(const MachineFunction &MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index f08195e..bee76a2 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -28,7 +28,6 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
 using namespace llvm;
@@ -179,14 +178,6 @@
   return CalleeSavedRegClasses;
 }
 
-BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(Alpha::R15);
-  Reserved.set(Alpha::R30);
-  Reserved.set(Alpha::R31);
-  return Reserved;
-}
-
 //===----------------------------------------------------------------------===//
 // Stack Frame Processing methods
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h
index 4629aaa..5c3f8ec 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -49,8 +49,6 @@
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-
   bool hasFP(const MachineFunction &MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index f5f8226..cb9918f 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -28,7 +28,6 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 using namespace llvm;
 
@@ -107,19 +106,6 @@
   return CalleeSavedRegClasses;
 }
 
-BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(IA64::r0);
-  Reserved.set(IA64::r1);
-  Reserved.set(IA64::r2);
-  Reserved.set(IA64::r5);
-  Reserved.set(IA64::r12);
-  Reserved.set(IA64::r13);
-  Reserved.set(IA64::r22);
-  Reserved.set(IA64::rp);
-  return Reserved;
-}
-
 //===----------------------------------------------------------------------===//
 // Stack Frame Processing methods
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h
index 9a97712..42a2567 100644
--- a/lib/Target/IA64/IA64RegisterInfo.h
+++ b/lib/Target/IA64/IA64RegisterInfo.h
@@ -48,8 +48,6 @@
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-
   bool hasFP(const MachineFunction &MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index 0803920..7caaae9 100644
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -41,7 +41,7 @@
     const TargetRegisterClass *RC = *I;
     for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
            E = RC->allocation_order_end(MF); I != E; ++I)
-      Allocatable.set(*I);
+      Allocatable[*I] = true;
   }
   return Allocatable;
 }
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7553634..3370c36 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -34,7 +34,6 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
 using namespace llvm;
@@ -339,35 +338,6 @@
                                Darwin32_CalleeSavedRegClasses;
 }
 
-// needsFP - Return true if the specified function should have a dedicated frame
-// pointer register.  This is true if the function has variable sized allocas or
-// if frame pointer elimination is disabled.
-//
-static bool needsFP(const MachineFunction &MF) {
-  const MachineFrameInfo *MFI = MF.getFrameInfo();
-  return NoFramePointerElim || MFI->hasVarSizedObjects();
-}
-
-BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(PPC::R0);
-  Reserved.set(PPC::R1);
-  Reserved.set(PPC::LR);
-  // In Linux, r2 is reserved for the OS.
-  if (!Subtarget.isDarwin())
-    Reserved.set(PPC::R2);
-  // On PPC64, r13 is the thread pointer.  Never allocate this register.
-  // Note that this is overconservative, as it also prevents allocation of
-  // R31 when the FP is not needed.
-  if (Subtarget.isPPC64()) {
-    Reserved.set(PPC::R13);
-    Reserved.set(PPC::R31);
-  }
-  if (needsFP(MF))
-    Reserved.set(PPC::R31);
-  return Reserved;
-}
-
 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
 /// copy instructions, turning them into load/store instructions.
 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
@@ -428,6 +398,15 @@
 // Stack Frame Processing methods
 //===----------------------------------------------------------------------===//
 
+// needsFP - Return true if the specified function should have a dedicated frame
+// pointer register.  This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+//
+static bool needsFP(const MachineFunction &MF) {
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
+  return NoFramePointerElim || MFI->hasVarSizedObjects();
+}
+
 // hasFP - Return true if the specified function actually has a dedicated frame
 // pointer register.  This is true if the function needs a frame pointer and has
 // a non-zero stack size.
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index 6c30f6b..f8344de 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -58,8 +58,6 @@
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-
   /// targetHandlesStackFrameRounding - Returns true if the target is
   /// responsible for rounding up the stack frame (probably at emitPrologue
   /// time).
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index dab0b10..3cb5e50 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -20,7 +20,6 @@
 #include "llvm/CodeGen/MachineLocation.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Type.h"
-#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 using namespace llvm;
 
@@ -117,22 +116,6 @@
   return CalleeSavedRegs;
 }
 
-BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(SP::G2);
-  Reserved.set(SP::G3);
-  Reserved.set(SP::G4);
-  Reserved.set(SP::O6);
-  Reserved.set(SP::I6);
-  Reserved.set(SP::I7);
-  Reserved.set(SP::G0);
-  Reserved.set(SP::G5);
-  Reserved.set(SP::G6);
-  Reserved.set(SP::G7);
-  return Reserved;
-}
-
-
 const TargetRegisterClass* const*
 SparcRegisterInfo::getCalleeSavedRegClasses() const {
   static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 763156a..6f80339 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -52,8 +52,6 @@
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-
   bool hasFP(const MachineFunction &MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 65e847e..50fb091 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -31,7 +31,6 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 using namespace llvm;
 
@@ -884,21 +883,6 @@
   return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
 }
 
-BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(X86::RSP);
-  Reserved.set(X86::ESP);
-  Reserved.set(X86::SP);
-  Reserved.set(X86::SPL);
-  if (hasFP(MF)) {
-    Reserved.set(X86::RBP);
-    Reserved.set(X86::EBP);
-    Reserved.set(X86::BP);
-    Reserved.set(X86::BPL);
-  }
-  return Reserved;
-}
-
 //===----------------------------------------------------------------------===//
 // Stack Frame Processing methods
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index d504675..0066fb6 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -78,12 +78,6 @@
   /// length of this list match the getCalleeSavedRegs() list.
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
-  /// getReservedRegs - Returns a bitset indexed by physical register number
-  /// indicating if a register is a special register that has particular uses and
-  /// should be considered unavailable at all times, e.g. SP, RA. This is used by
-  /// register scavenger to determine what registers are free.
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-
   bool hasFP(const MachineFunction &MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,