Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55777 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 51ef25a..f46777c 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -157,10 +157,10 @@
X86AddressMode AM;
if (Op1)
// Address is in register.
- AM.Base.Reg = Op0;
+ AM.Base.Reg = Op1;
else
AM.GV = cast<GlobalValue>(V);
- addFullAddress(BuildMI(MBB, TII.get(Opc)), AM);
+ addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0);
return true;
}
@@ -255,6 +255,8 @@
default: break;
case Instruction::Load:
return X86SelectLoad(I);
+ case Instruction::Store:
+ return X86SelectStore(I);
}
return false;