MSR (Move to Special Register from ARM core register) requires a mask to specify
what fields of the CPSR or SPSR are affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 77714bb..2fc7d2f 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2637,9 +2637,9 @@
let Inst{12} = 0;
}
-// FIXME: mask is ignored for the time being.
// Rn = Inst{19-16}
-def t2MSR : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src",
+def t2MSR : T2I<(outs), (ins GPR:$src, i32imm:$mask), NoItinerary, "msr",
+ "\tcpsr${mask:msr}, $src",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
@@ -2649,9 +2649,9 @@
let Inst{12} = 0;
}
-// FIXME: mask is ignored for the time being.
// Rn = Inst{19-16}
-def t2MSRsys : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tspsr, $src",
+def t2MSRsys : T2I<(outs), (ins GPR:$src, i32imm:$mask), NoItinerary, "msr",
+ "\tspsr${mask:msr}, $src",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;