add a little peephole optimization. This allows us to codegen:
int a(short i) {
return i & 1;
}
as
_a:
andi. r3, r3, 1
blr
instead of:
_a:
rlwinm r2, r3, 0, 16, 31
andi. r3, r2, 1
blr
on ppc. It should also help the other risc targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21189 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 765ff1b..74e807c 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -766,6 +766,17 @@
if (!C2) return N2; // X and 0 -> 0
if (N2C->isAllOnesValue())
return N1; // X and -1 -> X
+
+ // and (zero_extend_inreg x:16:32), 1 -> and x, 1
+ if (N1.getOpcode() == ISD::ZERO_EXTEND_INREG ||
+ N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ // If we are masking out the part of our input that was extended, just
+ // mask the input to the extension directly.
+ unsigned ExtendBits =
+ MVT::getSizeInBits(cast<MVTSDNode>(N1)->getExtraValueType());
+ if ((C2 & (~0ULL << ExtendBits)) == 0)
+ return getNode(ISD::AND, VT, N1.getOperand(0), N2);
+ }
break;
case ISD::OR:
if (!C2)return N1; // X or 0 -> X