commit a399d698a84ffd22c7d1f121c24cbc147c6f4e06
author Daniel Sanders <daniel.sanders@imgtec.com> Mon Sep 23 13:40:21 2013 +0000
committer Daniel Sanders <daniel.sanders@imgtec.com> Mon Sep 23 13:40:21 2013 +0000
tree 8cbb7447ccf7082e18f6723808af0d8b65320579
parent 915432ca1306d10453c9eb523cbc4b257642f62a

[mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191198 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsSEISelLowering.cpp

diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index ca3e06c..610b8bf 100644
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -166,6 +166,7 @@
   setOperationAction(ISD::ADD, Ty, Legal);
   setOperationAction(ISD::AND, Ty, Legal);
   setOperationAction(ISD::CTLZ, Ty, Legal);
+  setOperationAction(ISD::CTPOP, Ty, Legal);
   setOperationAction(ISD::MUL, Ty, Legal);
   setOperationAction(ISD::OR, Ty, Legal);
   setOperationAction(ISD::SDIV, Ty, Legal);
@@ -1012,6 +1013,11 @@
   }
   case Intrinsic::mips_or_v:
     return lowerMSABinaryIntr(Op, DAG, ISD::OR);
+  case Intrinsic::mips_pcnt_b:
+  case Intrinsic::mips_pcnt_h:
+  case Intrinsic::mips_pcnt_w:
+  case Intrinsic::mips_pcnt_d:
+    return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
   case Intrinsic::mips_sll_b:
   case Intrinsic::mips_sll_h:
   case Intrinsic::mips_sll_w: