commit a3d82ce19fd825cbf3bf85b5969424217fc40b45
author Andrew Trick <atrick@apple.com> Sat Jun 15 04:50:06 2013 +0000
committer Andrew Trick <atrick@apple.com> Sat Jun 15 04:50:06 2013 +0000
tree 929b456a7903435946a54f91c04a502c0f0438d3
parent a5ce5f36d3a1e312304e8312ca64a1342f5f55a6

Support BufferSize on ProcResGroup for unified MOp schedulers.

And add Sandybridge/Haswell resource buffers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeGenSchedule.cpp

diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp
index 8015e34..85eee5f 100644
--- a/utils/TableGen/CodeGenSchedule.cpp
+++ b/utils/TableGen/CodeGenSchedule.cpp
@@ -1476,6 +1476,19 @@
     Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
     addReadAdvance(*RAI, getProcModel(ModelDef).Index);
   }
+  // Add ProcResGroups that are defined within this processor model, which may
+  // not be directly referenced but may directly specify a buffer size.
+  RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");
+  for (RecIter RI = ProcResGroups.begin(), RE = ProcResGroups.end();
+       RI != RE; ++RI) {
+    if (!(*RI)->getValueInit("SchedModel")->isComplete())
+      continue;
+    CodeGenProcModel &PM = getProcModel((*RI)->getValueAsDef("SchedModel"));
+    RecIter I = std::find(PM.ProcResourceDefs.begin(),
+                          PM.ProcResourceDefs.end(), *RI);
+    if (I == PM.ProcResourceDefs.end())
+      PM.ProcResourceDefs.push_back(*RI);
+  }
   // Finalize each ProcModel by sorting the record arrays.
   for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
     CodeGenProcModel &PM = ProcModels[PIdx];

utils/TableGen/CodeGenSchedule.h

diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h
index 2e0a149..fa964cf 100644
--- a/utils/TableGen/CodeGenSchedule.h
+++ b/utils/TableGen/CodeGenSchedule.h
@@ -266,11 +266,14 @@
     return ProcModels[I->second];
   }
 
-  const CodeGenProcModel &getProcModel(Record *ModelDef) const {
+  CodeGenProcModel &getProcModel(Record *ModelDef) {
     ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
     assert(I != ProcModelMap.end() && "missing machine model");
     return ProcModels[I->second];
   }
+  const CodeGenProcModel &getProcModel(Record *ModelDef) const {
+    return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
+  }
 
   // Iterate over the unique processor models.
   typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;

utils/TableGen/SubtargetEmitter.cpp

diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index c6ce35f..81bb6f8 100644
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -634,14 +634,11 @@
     Record *SuperDef = 0;
     unsigned SuperIdx = 0;
     unsigned NumUnits = 0;
-    int BufferSize = -1;
+    int BufferSize = PRDef->getValueAsInt("BufferSize");
     if (PRDef->isSubClassOf("ProcResGroup")) {
       RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
       for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end();
            RUI != RUE; ++RUI) {
-        int BuffSz = (*RUI)->getValueAsInt("BufferSize");
-        if (!NumUnits || (unsigned)BufferSize < (unsigned)BuffSz)
-          BufferSize = BuffSz;
         NumUnits += (*RUI)->getValueAsInt("NumUnits");
       }
     }
@@ -653,7 +650,6 @@
         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
       }
       NumUnits = PRDef->getValueAsInt("NumUnits");
-      BufferSize = PRDef->getValueAsInt("BufferSize");
     }
     // Emit the ProcResourceDesc
     if (i+1 == e)