Add reg-imm tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84705 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/MSP430/Inst16ri.ll b/test/CodeGen/MSP430/Inst16ri.ll
new file mode 100644
index 0000000..5115a23
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst16ri.ll
@@ -0,0 +1,37 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i16 @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.w #1, r15
+ ret i16 1
+}
+
+define i16 @add(i16 %a, i16 %b) nounwind {
+; CHECK: add:
+; CHECK: add.w #1, r15
+ %1 = add i16 %a, 1
+ ret i16 %1
+}
+
+define i16 @and(i16 %a, i16 %b) nounwind {
+; CHECK: and:
+; CHECK: and.w #1, r15
+ %1 = and i16 %a, 1
+ ret i16 %1
+}
+
+define i16 @bis(i16 %a, i16 %b) nounwind {
+; CHECK: bis:
+; CHECK: bis.w #1, r15
+ %1 = or i16 %a, 1
+ ret i16 %1
+}
+
+define i16 @xor(i16 %a, i16 %b) nounwind {
+; CHECK: xor:
+; CHECK: xor.w #1, r15
+ %1 = xor i16 %a, 1
+ ret i16 %1
+}