Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 713cc2e..27b0ed2 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1357,6 +1357,7 @@
case MVT::v4i16: Opc = ARM::VLD2d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2d32; break;
+ case MVT::v1i64: Opc = ARM::VLD2d64; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 334f496..11117cc 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -193,6 +193,9 @@
def VLD2d8 : VLD2D<0b0000, "vld2.8">;
def VLD2d16 : VLD2D<0b0100, "vld2.16">;
def VLD2d32 : VLD2D<0b1000, "vld2.32">;
+def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
+ (ins addrmode6:$addr), IIC_VLD1,
+ "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>;
def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
def VLD2q16 : VLD2Q<0b0100, "vld2.16">;
diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp
index 0c167a1..e795e1a 100644
--- a/lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/lib/Target/ARM/NEONPreAllocPass.cpp
@@ -49,6 +49,7 @@
case ARM::VLD2d8:
case ARM::VLD2d16:
case ARM::VLD2d32:
+ case ARM::VLD2d64:
case ARM::VLD2LNd8:
case ARM::VLD2LNd16:
case ARM::VLD2LNd32: