Replace some std::vectors that showed up in heap profiling with
SmallVectors. Change the signature of TargetLowering::LowerArguments
to avoid returning a vector by value, and update the two targets
which still use this directly, Sparc and IA64, accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52917 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 235f4f2..8822a17 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -964,8 +964,9 @@
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
- virtual std::vector<SDOperand>
- LowerArguments(Function &F, SelectionDAG &DAG);
+ virtual void
+ LowerArguments(Function &F, SelectionDAG &DAG,
+ SmallVectorImpl<SDOperand>& ArgValues);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call. This returns a pair of operands. The first element is the
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index e8537d2..1124f37 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -474,7 +474,7 @@
/// them up and then emit token factor nodes when possible. This allows us to
/// get simple disambiguation between loads without worrying about alias
/// analysis.
- std::vector<SDOperand> PendingLoads;
+ SmallVector<SDOperand, 8> PendingLoads;
/// PendingExports - CopyToReg nodes that copy values to virtual registers
/// for export to other blocks need to be emitted before any terminator
@@ -4612,16 +4612,16 @@
/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
/// integrated into SDISel.
-std::vector<SDOperand>
-TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
+void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
+ SmallVectorImpl<SDOperand> &ArgValues) {
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 3+16> Ops;
Ops.push_back(DAG.getRoot());
Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
// Add one result value for each formal argument.
- std::vector<MVT> RetVals;
+ SmallVector<MVT, 16> RetVals;
unsigned j = 1;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++j) {
@@ -4699,7 +4699,6 @@
DAG.setRoot(SDOperand(Result, NumArgRegs));
// Set up the return result vector.
- Ops.clear();
unsigned i = 0;
unsigned Idx = 1;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
@@ -4722,12 +4721,11 @@
else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
AssertOp = ISD::AssertZext;
- Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
- AssertOp));
+ ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
+ AssertOp));
}
}
assert(i == NumArgRegs && "Argument register count mismatch!");
- return Ops;
}
@@ -4951,7 +4949,8 @@
Function &F = *LLVMBB->getParent();
FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
SDOperand OldRoot = SDL.DAG.getRoot();
- std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
+ SmallVector<SDOperand, 16> Args;
+ TLI.LowerArguments(F, SDL.DAG, Args);
unsigned a = 0;
for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 8b711d8..710cd0c 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -143,9 +143,8 @@
return MVT::i1;
}
-std::vector<SDOperand>
-IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
- std::vector<SDOperand> ArgValues;
+void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
+ SmallVectorImpl<SDOperand> &ArgValues) {
//
// add beautiful description of IA64 stack frame format
// here (from intel 24535803.pdf most likely)
@@ -300,8 +299,6 @@
MF.getRegInfo().addLiveOut(IA64::F8);
break;
}
-
- return ArgValues;
}
std::pair<SDOperand, SDOperand>
diff --git a/lib/Target/IA64/IA64ISelLowering.h b/lib/Target/IA64/IA64ISelLowering.h
index b26c822..54f6c2e 100644
--- a/lib/Target/IA64/IA64ISelLowering.h
+++ b/lib/Target/IA64/IA64ISelLowering.h
@@ -53,8 +53,8 @@
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
- virtual std::vector<SDOperand>
- LowerArguments(Function &F, SelectionDAG &DAG);
+ virtual void LowerArguments(Function &F, SelectionDAG &DAG,
+ SmallVectorImpl<SDOperand> &ArgValues);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index 48b4fec..fd60296 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -74,11 +74,11 @@
/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
/// either one or two GPRs, including FP values. TODO: we should pass FP values
/// in FP registers for fastcc functions.
-std::vector<SDOperand>
-SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
+void
+SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
+ SmallVectorImpl<SDOperand> &ArgValues) {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- std::vector<SDOperand> ArgValues;
static const unsigned ArgRegs[] = {
SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
@@ -221,8 +221,6 @@
if (!OutChains.empty())
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
&OutChains[0], OutChains.size()));
-
- return ArgValues;
}
static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h
index 023ea93..2257304 100644
--- a/lib/Target/Sparc/SparcISelLowering.h
+++ b/lib/Target/Sparc/SparcISelLowering.h
@@ -57,8 +57,8 @@
const SelectionDAG &DAG,
unsigned Depth = 0) const;
- virtual std::vector<SDOperand>
- LowerArguments(Function &F, SelectionDAG &DAG);
+ virtual void LowerArguments(Function &F, SelectionDAG &DAG,
+ SmallVectorImpl<SDOperand> &ArgValues);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);