commit a47c6c37034f4e57bc8187e959da4eadb6e24afa
author Duncan Sands <baldrick@free.fr> Tue Jun 17 03:24:13 2008 +0000
committer Duncan Sands <baldrick@free.fr> Tue Jun 17 03:24:13 2008 +0000
tree 256521a2841576b68dd9956ba2628dac1f6a1d2b
parent 851bc0453350254cd45a91b6af9592003562d707

Fix spelling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52381 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a55f904..50799d1 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4283,7 +4283,7 @@
       // Copy the output from the appropriate register.  Find a register that
       // we can use.
       if (OpInfo.AssignedRegs.Regs.empty()) {
-        cerr << "Couldn't allocate output reg for contraint '"
+        cerr << "Couldn't allocate output reg for constraint '"
              << OpInfo.ConstraintCode << "'!\n";
         exit(1);
       }