commit a596f8c3aaeba95fa20706bb0c441ff1b3afc8b8
author Misha Brukman <brukman+llvm@gmail.com> Tue Jul 13 15:35:45 2004 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Tue Jul 13 15:35:45 2004 +0000
tree 71dbe533c249090799b2f3adfb858df9b69b0b4c
parent b3366bc37e81a27d2d830df61fc1425c78523eac

* Specify that FP arith options have 3 operands
* Correctly load FP constants from the constant pool, should be refactored


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14799 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC32ISelSimple.cpp

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 7d9e7cc..bf4ce52 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -1615,16 +1615,16 @@
       { PPC32::FADD,  PPC32::FSUB,  PPC32::FMUL,  PPC32::FDIV },   // Double
     };
 
-    unsigned Op1Reg = getReg(Op1C);
     unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
+    unsigned Op1Reg = getReg(Op1C, BB, IP);
     unsigned Op0r = getReg(Op0, BB, IP);
-    BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(Op1Reg);
+    BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1Reg);
     return;
   }
   
   // Special case: R1 = op <const fp>, R2
-  if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
-    if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
+  if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
+    if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
       // -0.0 - X === -X
       unsigned op1Reg = getReg(Op1, BB, IP);
       BuildMI(*BB, IP, PPC32::FNEG, 1, DestReg).addReg(op1Reg);
@@ -1634,22 +1634,19 @@
 
       // Create a constant pool entry for this constant.
       MachineConstantPool *CP = F->getConstantPool();
-      unsigned CPI = CP->getConstantPoolIndex(CFP);
-      const Type *Ty = CFP->getType();
+      unsigned CPI = CP->getConstantPoolIndex(Op0C);
+      const Type *Ty = Op0C->getType();
+      assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
 
       static const unsigned OpcodeTab[][4] = {
         { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS },  // Float
         { PPC32::FADD,  PPC32::FSUB,  PPC32::FMUL,  PPC32::FDIV },   // Double
       };
 
-      assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
-      unsigned TempReg = makeAnotherReg(Ty);
-      unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
-      addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
-
       unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
-      unsigned Op1r = getReg(Op1, BB, IP);
-      BuildMI(*BB, IP, Opcode, DestReg).addReg(TempReg).addReg(Op1r);
+      unsigned Op0Reg = getReg(Op0C, BB, IP);
+      unsigned Op1Reg = getReg(Op1, BB, IP);
+      BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
       return;
     }