Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:
- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
compiles and generates the right code. More work still needs to be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/CellSDKIntrinsics.td b/lib/Target/CellSPU/CellSDKIntrinsics.td
index 2f453b1..5d759a4 100644
--- a/lib/Target/CellSPU/CellSDKIntrinsics.td
+++ b/lib/Target/CellSPU/CellSDKIntrinsics.td
@@ -210,20 +210,20 @@
(SHLIv4i32 VECREG:$rA, uimm7:$val)>;
def CellSDKshlqbi:
- Pat<(int_spu_si_shlqbi VECREG:$rA, VECREG:$rB),
- (SHLQBIvec VECREG:$rA, VECREG:$rB)>;
+ Pat<(int_spu_si_shlqbi VECREG:$rA, R32C:$rB),
+ (SHLQBIv16i8 VECREG:$rA, R32C:$rB)>;
def CellSDKshlqii:
Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val),
- (SHLQBIIvec VECREG:$rA, uimm7:$val)>;
+ (SHLQBIIv16i8 VECREG:$rA, uimm7:$val)>;
def CellSDKshlqby:
- Pat<(int_spu_si_shlqby VECREG:$rA, VECREG:$rB),
- (SHLQBYvec VECREG:$rA, VECREG:$rB)>;
+ Pat<(int_spu_si_shlqby VECREG:$rA, R32C:$rB),
+ (SHLQBYv16i8 VECREG:$rA, R32C:$rB)>;
def CellSDKshlqbyi:
Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val),
- (SHLQBYIvec VECREG:$rA, uimm7:$val)>;
+ (SHLQBYIv16i8 VECREG:$rA, uimm7:$val)>;
//===----------------------------------------------------------------------===//
// Branch/compare intrinsics: