Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index e66192a..f28af15 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -92,7 +92,8 @@
else if (OpR->isSubClassOf("PointerLikeRegClass"))
Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
else
- Res += "0, ";
+ // -1 means the operand does not have a fixed register class.
+ Res += "-1, ";
// Fill in applicable flags.
Res += "0";
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 2695747..a3ca0bc 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -96,7 +96,7 @@
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
if (i) OS << ",\n";
OS << " " << RegisterClasses[i].getName() << "RegClassID";
- OS << " = " << (i+1);
+ OS << " = " << i;
}
OS << "\n };\n\n";