commit a656b63ee4d5b0e3f4d26a55dd4cc69795746684
author Bill Wendling <isanbard@gmail.com> Tue Mar 01 01:00:59 2011 +0000
committer Bill Wendling <isanbard@gmail.com> Tue Mar 01 01:00:59 2011 +0000
tree 207aa0386e59701c56483a84bcc30708bb82795d
parent f291ab2fbaa5ed1cfa20ca47e8dece1040a5065b

Narrow right shifts need to encode their immediates differently from a normal
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/EDEmitter.cpp

diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index 020a4a3..b3deb84 100644
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -598,6 +598,9 @@
   IMM("t2adrlabel");
   IMM("shift_imm");
   IMM("neon_vcvt_imm32");
+  IMM("nsr16_imm");
+  IMM("nsr32_imm");
+  IMM("nsr64_imm");
 
   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
   MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?