Improve ISD::Constant codegen.
Now for int foo() { return -1; } we generate:
_foo:
li r3, -1
blr
instead of
_foo:
lis r2, -1
ori r3, r2, 65535
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 18eaa9f..5320595 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -277,15 +277,18 @@
case ISD::Constant: {
assert(N->getValueType(0) == MVT::i32);
unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
- if ((unsigned)(short)v == v) {
- CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
- break;
- } else {
- SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
- getI32Imm(unsigned(v) >> 16));
+ unsigned Hi = HA16(v);
+ unsigned Lo = Lo16(v);
+ if (Hi && Lo) {
+ SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
+ getI32Imm(v >> 16));
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
- break;
+ } else if (Lo) {
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
+ } else {
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
}
+ break;
}
case ISD::SIGN_EXTEND_INREG:
switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
@@ -412,12 +415,13 @@
Select(N->getOperand(1)));
break;
case ISD::AND: {
- unsigned Imm, SH, MB, ME;
+ unsigned Imm;
// If this is an and of a value rotated between 0 and 31 bits and then and'd
// with a mask, emit rlwinm
if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
isShiftedMask_32(~Imm))) {
SDOperand Val;
+ unsigned SH, MB, ME;
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
Val = Select(N->getOperand(0).getOperand(0));
} else {
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 6eddcc4..1ffa6dc 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1736,7 +1736,7 @@
assert(N.getValueType() == MVT::i32 &&
"Only i32 constants are legal on this target!");
int v = (int)cast<ConstantSDNode>(N)->getValue();
- unsigned Hi = Hi16(v);
+ unsigned Hi = HA16(v);
unsigned Lo = Lo16(v);
if (Hi && Lo) {
Tmp1 = MakeIntReg();