commit a6ad5bea544dc96b2d66b1bd3070dfaf6b6ab16e
author Anton Korobeynikov <asl@math.spbu.ru> Mon Aug 03 08:14:14 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Mon Aug 03 08:14:14 2009 +0000
tree 2d87441df68faa4a4ec13e532baed9f8ff808345
parent 78c3160526f49bddf6040a23a73594720c264a5c

Perform bitconvert to proper type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77965 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a46ec1c..298a5a8 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1448,8 +1448,7 @@
         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
                                DAG.getValueType(VA.getValVT()));
       else if (VA.getLocInfo() == CCValAssign::BCvt)
-        ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, ArgValue,
-                               DAG.getValueType(VA.getValVT()));
+        ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
 
       if (VA.isExtInLoc()) {
         // Handle MMX values passed in XMM regs.