Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
Add an extra run with -regalloc=basic to keep them honest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/Mips/2008-08-06-Alloca.ll b/test/CodeGen/Mips/2008-08-06-Alloca.ll
index 7be7974..5c55137 100644
--- a/test/CodeGen/Mips/2008-08-06-Alloca.ll
+++ b/test/CodeGen/Mips/2008-08-06-Alloca.ll
@@ -1,4 +1,9 @@
-; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
+; RUN: llc < %s -march=mips -regalloc=linearscan | grep {subu.*sp} | count 2
+
+; This test depends on a linearscan optimization, joining copies from reserved
+; registers.
+; After coalescing, copies from %SP remain.
+; They are handled by RALinScan::attemptTrivialCoalescing
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"
diff --git a/test/CodeGen/Mips/2010-07-20-Select.ll b/test/CodeGen/Mips/2010-07-20-Select.ll
index a277149..e5e2c54 100644
--- a/test/CodeGen/Mips/2010-07-20-Select.ll
+++ b/test/CodeGen/Mips/2010-07-20-Select.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
+; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
; Fix PR7473
define i32 @main() nounwind readnone {
@@ -9,12 +10,12 @@
volatile store i32 0, i32* %c, align 4
%0 = volatile load i32* %a, align 4 ; <i32> [#uses=1]
%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 0
+; CHECK: addiu $[[R1:[0-9]+]], $zero, 0
%iftmp.0.0 = select i1 %1, i32 3, i32 0 ; <i32> [#uses=1]
%2 = volatile load i32* %c, align 4 ; <i32> [#uses=1]
%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 3
-; CHECK: addu $2, $3, $4
+; CHECK: addiu $[[R1]], $zero, 3
+; CHECK: addu $2, ${{.}}, $[[R1]]
%iftmp.2.0 = select i1 %3, i32 0, i32 5 ; <i32> [#uses=1]
%4 = add nsw i32 %iftmp.2.0, %iftmp.0.0 ; <i32> [#uses=1]
ret i32 %4
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 7d3e025..8329c89 100755
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -1,10 +1,11 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
-; CHECK: lw $3, %got(i3)($gp)
-; CHECK: addiu $5, $gp, %got(i1)
+; CHECK: lw ${{[0-9]+}}, %got(i3)($gp)
+; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
define i32* @cmov1(i32 %s) nounwind readonly {
entry:
%tobool = icmp ne i32 %s, 0
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll
index 50b43b4..6601d25 100644
--- a/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s
; All test functions do the same thing - they return the first variable
@@ -56,14 +57,14 @@
; CHECK: va2:
; CHECK: addiu $sp, $sp, -40
-; CHECK: addiu $2, $sp, 44
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
; CHECK: sw $5, 44($sp)
; CHECK: sw $6, 48($sp)
; CHECK: sw $7, 52($sp)
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $3, $3, $5
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -109,11 +110,11 @@
; CHECK: addiu $sp, $sp, -48
; CHECK: sw $6, 56($sp)
; CHECK: sw $7, 60($sp)
-; CHECK: addiu $3, $sp, 56
-; CHECK: addiu $6, $3, 7
-; CHECK: addiu $7, $zero, -8
-; CHECK: and $2, $6, $7
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -165,11 +166,11 @@
; CHECK: va6:
; CHECK: addiu $sp, $sp, -48
; CHECK: sw $7, 60($sp)
-; CHECK: addiu $2, $sp, 60
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $3, $3, $4
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -215,11 +216,11 @@
; CHECK: va8:
; CHECK: addiu $sp, $sp, -48
-; CHECK: addiu $3, $sp, 64
-; CHECK: addiu $4, $3, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $2, $4, $5
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -269,9 +270,9 @@
; CHECK: va10:
; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $3, $sp, 76
-; CHECK: addiu $2, $3, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $2, $2, $4
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 76
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}