commit a7a5854f1c3710f4bedf069be4771b81e449f2a3
author Chris Lattner <sabre@nondot.org> Fri Jun 16 17:34:12 2006 +0000
committer Chris Lattner <sabre@nondot.org> Fri Jun 16 17:34:12 2006 +0000
tree 438c2801d45b3995eed10e57be580d2d2797f172
parent 6557f186896b9a4f57ea354ee04e0c74c389e0e1

Rename some subtarget features.  A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCSubtarget.cpp

diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
index 607771b..b228ba7 100644
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -73,8 +73,8 @@
   : StackAlignment(16)
   , InstrItins()
   , IsGigaProcessor(false)
-  , Is64Bit(false)
-  , Has64BitRegs(false)
+  , Has64BitSupport(false)
+  , Use64BitRegs(false)
   , HasAltivec(false)
   , HasFSQRT(false)
   , HasSTFIWX(false)