commit a7c7b9dccba2c14a93f0f9a29490f1df4f9b4080
author Wesley Peck <peckw@wesleypeck.com> Sun Dec 12 22:02:31 2010 +0000
committer Wesley Peck <peckw@wesleypeck.com> Sun Dec 12 22:02:31 2010 +0000
tree e93e3c9996bb78d930573677615bc97f30f1e817
parent d713acb63105f55ef5ed0f3a499da81c3eeacd49

The ADD and ADDK (and all variants) instructions where flip-flopped in the MBlaze backend. This bug fix makes 64-bit math work on the MBlaze backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121649 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/MBlaze/MBlazeISelLowering.cpp

diff --git a/lib/Target/MBlaze/MBlazeISelLowering.cpp b/lib/Target/MBlaze/MBlazeISelLowering.cpp
index fb6fb54..ad7222a 100644
--- a/lib/Target/MBlaze/MBlazeISelLowering.cpp
+++ b/lib/Target/MBlaze/MBlazeISelLowering.cpp
@@ -268,7 +268,7 @@
       .addImm(31);
 
     unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
-    BuildMI(BB, dl, TII->get(MBlaze::ADDI), IVAL)
+    BuildMI(BB, dl, TII->get(MBlaze::ADDIK), IVAL)
       .addReg(MI->getOperand(1).getReg())
       .addImm(0);
 
@@ -297,7 +297,7 @@
     else
         llvm_unreachable("Cannot lower unknown shift instruction");
 
-    BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT)
+    BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
       .addReg(SAMT)
       .addImm(-1);