recognize ppc's blr instruction as predicated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index f8410c1..5893a58 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -335,6 +335,7 @@
isLoad = R->getValueAsBit("isLoad");
isStore = R->getValueAsBit("isStore");
isTwoAddress = R->getValueAsBit("isTwoAddress");
+ isPredicated = false; // set below.
isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
isCommutable = R->getValueAsBit("isCommutable");
isTerminator = R->getValueAsBit("isTerminator");
@@ -381,6 +382,7 @@
if (unsigned NumArgs = MIOpInfo->getNumArgs())
NumOps = NumArgs;
+ isPredicated |= Rec->isSubClassOf("PredicateOperand");
} else if (Rec->getName() == "variable_ops") {
hasVariableNumberOfOperands = true;
continue;