more general matching of the MVN instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32484 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index a796431..6abc097 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -849,13 +849,17 @@
case ISD::Constant: {
uint32_t val = cast<ConstantSDNode>(N)->getValue();
if(!isRotInt8Immediate(val)) {
- if (isRotInt8Immediate(~val))
- return false; //use MVN
- Constant *C = ConstantInt::get(Type::UIntTy, val);
- int alignment = 2;
- SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
- SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32);
- SDNode *n = CurDAG->getTargetNode(ARM::LDR, MVT::i32, Addr, Z);
+ SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32);
+ SDNode *n;
+ if (isRotInt8Immediate(~val)) {
+ SDOperand C = CurDAG->getTargetConstant(~val, MVT::i32);
+ n = CurDAG->getTargetNode(ARM::MVN, MVT::i32, C, Z, Z);
+ } else {
+ Constant *C = ConstantInt::get(Type::UIntTy, val);
+ int alignment = 2;
+ SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
+ n = CurDAG->getTargetNode(ARM::LDR, MVT::i32, Addr, Z);
+ }
Arg = SDOperand(n, 0);
} else
Arg = CurDAG->getTargetConstant(val, MVT::i32);
@@ -887,25 +891,6 @@
return true;
}
-bool ARMDAGToDAGISel::SelectAddrMode1a(SDOperand Op,
- SDOperand N,
- SDOperand &Arg,
- SDOperand &Shift,
- SDOperand &ShiftType) {
- if (N.getOpcode() != ISD::Constant)
- return false;
-
- uint32_t val = ~cast<ConstantSDNode>(N)->getValue();
- if(!isRotInt8Immediate(val))
- return false;
-
- Arg = CurDAG->getTargetConstant(val, MVT::i32);
- Shift = CurDAG->getTargetConstant(0, MVT::i32);
- ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
-
- return true;
-}
-
bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
SDOperand &Arg, SDOperand &Offset) {
//TODO: complete and cleanup!
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 2d1bfc0..4be2b74 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -18,11 +18,6 @@
let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
}
-def op_addr_mode1a : Operand<iPTR> {
- let PrintMethod = "printAddrMode1";
- let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
-}
-
def op_addr_mode2 : Operand<iPTR> {
let PrintMethod = "printAddrMode2";
let MIOperandInfo = (ops ptr_rc, i32imm);
@@ -38,9 +33,6 @@
def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
[]>;
-//Addressing Mode 1a: MVN hack
-def addr_mode1a : ComplexPattern<iPTR, 3, "SelectAddrMode1a", [imm], []>;
-
//Addressing Mode 2: Load and Store Word or Unsigned Byte
def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
@@ -201,9 +193,6 @@
def MVN : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
"mvn $dst, $src", [(set IntRegs:$dst, (not addr_mode1:$src))]>;
-def MVN2 : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
- "mvn $dst, $src", [(set IntRegs:$dst, addr_mode1a:$src)]>;
-
def ADD : Addr1BinOp<"add", add>;
def ADCS : Addr1BinOp<"adcs", adde>;
def ADDS : Addr1BinOp<"adds", addc>;