diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index cd2fc16..deda6d7 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -128,8 +128,8 @@
         if (!ArgLive) break;
           if (GPR_remaining > 0) {
             MF.addLiveIn(GPR[GPR_idx]);
-            argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
-                                                DAG.getRoot());
+            argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
+                                                GPR[GPR_idx], MVT::i32);
             if (ObjectVT != MVT::i32)
               argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
           } else {
@@ -141,14 +141,14 @@
           if (GPR_remaining > 0) {
             SDOperand argHi, argLo;
             MF.addLiveIn(GPR[GPR_idx]);
-            argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
+            argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
             // If we have two or more remaining argument registers, then both halves
             // of the i64 can be sourced from there.  Otherwise, the lower half will
             // have to come off the stack.  This can happen when an i64 is preceded
             // by 28 bytes of arguments.
             if (GPR_remaining > 1) {
               MF.addLiveIn(GPR[GPR_idx+1]);
-              argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
+              argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
             } else {
               int FI = MFI->CreateFixedObject(4, ArgOffset+4);
               SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
@@ -168,8 +168,8 @@
         if (!ArgLive) break;
           if (FPR_remaining > 0) {
             MF.addLiveIn(FPR[FPR_idx]);
-            argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
-                                                DAG.getRoot());
+            argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), 
+                                                FPR[FPR_idx], ObjectVT);
             --FPR_remaining;
             ++FPR_idx;
           } else {
@@ -217,7 +217,7 @@
     std::vector<SDOperand> MemOps;
     for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
       MF.addLiveIn(GPR[GPR_idx]);
-      SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
+      SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
                                     Val, FIN, DAG.getSrcValue(NULL));
       MemOps.push_back(Store);
@@ -298,8 +298,8 @@
     // Set up a copy of the stack pointer for use loading and storing any
     // arguments that may not fit in the registers available for argument
     // passing.
-    SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
-                                            DAG.getEntryNode());
+    SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
+                                            PPC::R1, MVT::i32);
     
     // Figure out which arguments are going to go in registers, and which in
     // memory.  Also, if this is a vararg function, floating point operations
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 4e674dc..680d558 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -808,11 +808,12 @@
   SDNode *Node = N.Val;
   MVT::ValueType DestType = N.getValueType();
 
-  if (Node->getOpcode() == ISD::CopyFromReg &&
-      (MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()) ||
-       cast<RegSDNode>(Node)->getReg() == PPC::R1))
+  if (Node->getOpcode() == ISD::CopyFromReg) {
+    unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     // Just use the specified register as our input.
-    return cast<RegSDNode>(Node)->getReg();
+    if (MRegisterInfo::isVirtualRegister(Reg) || Reg == PPC::R1)
+      return Reg;
+  }
 
   unsigned &Reg = ExprMap[N];
   if (Reg) return Reg;
@@ -1085,7 +1086,7 @@
     DestType = N.getValue(0).getValueType();
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
-    Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
+    Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     if (MVT::isInteger(DestType))
       BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
     else
@@ -1877,12 +1878,12 @@
     return;
   case ISD::CopyToReg:
     Select(N.getOperand(0));
-    Tmp1 = SelectExpr(N.getOperand(1));
-    Tmp2 = cast<RegSDNode>(N)->getReg();
+    Tmp1 = SelectExpr(N.getOperand(2));
+    Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
 
     if (Tmp1 != Tmp2) {
-      if (N.getOperand(1).getValueType() == MVT::f64 ||
-          N.getOperand(1).getValueType() == MVT::f32)
+      if (N.getOperand(2).getValueType() == MVT::f64 ||
+          N.getOperand(2).getValueType() == MVT::f32)
         BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
       else
         BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
@@ -1890,7 +1891,8 @@
     return;
   case ISD::ImplicitDef:
     Select(N.getOperand(0));
-    BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
+    BuildMI(BB, PPC::IMPLICIT_DEF, 0,
+            cast<RegisterSDNode>(N.getOperand(1))->getReg());
     return;
   case ISD::RET:
     switch (N.getNumOperands()) {