commit a92b2f3024fb3ce131097bbd3704965dc1fbdd6d
author Evan Cheng <evan.cheng@apple.com> Mon May 10 17:34:18 2010 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon May 10 17:34:18 2010 +0000
tree 9313bdaedf33b3d1ae2ec138b171424fc48a9571
parent 2b72505bf40454601b9cfce6e3e59f7838dba944

Model vld2 / vst2 with reg_sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/NEONPreAllocPass.cpp

diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp
index 4440611..a8df364 100644
--- a/lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/lib/Target/ARM/NEONPreAllocPass.cpp
@@ -360,7 +360,7 @@
         return false;
       RegSeq = UseMI;
     } else {
-      // Extracting from a Q register.
+      // Extracting from a Q or QQ register.
       MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
       if (!DefMI || !DefMI->isExtractSubreg())
         return false;
@@ -368,8 +368,11 @@
       if (LastSrcReg && LastSrcReg != VirtReg)
         return false;
       const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
-      if (RC != ARM::QPRRegisterClass)
-        return false;
+      if (NumRegs == 2) {
+        if (RC != ARM::QPRRegisterClass)
+          return false;
+      } else if (RC != ARM::QQPRRegisterClass)
+          return false;
       unsigned SubIdx = DefMI->getOperand(2).getImm();
       if (LastSubIdx && LastSubIdx != SubIdx-1)
         return false;