Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUAsmPrinter.cpp b/lib/Target/CellSPU/SPUAsmPrinter.cpp
index 46e7eec..257d623 100644
--- a/lib/Target/CellSPU/SPUAsmPrinter.cpp
+++ b/lib/Target/CellSPU/SPUAsmPrinter.cpp
@@ -83,7 +83,7 @@
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
- O << MO.getImmedValue();
+ O << MO.getImm();
} else {
printOp(MO);
}
@@ -98,7 +98,7 @@
void
printS7ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- int value = MI->getOperand(OpNo).getImmedValue();
+ int value = MI->getOperand(OpNo).getImm();
value = (value << (32 - 7)) >> (32 - 7);
assert((value >= -(1 << 8) && value <= (1 << 7) - 1)
@@ -109,7 +109,7 @@
void
printU7ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- unsigned int value = MI->getOperand(OpNo).getImmedValue();
+ unsigned int value = MI->getOperand(OpNo).getImm();
assert(value < (1 << 8) && "Invalid u7 argument");
O << value;
}
@@ -117,7 +117,7 @@
void
printMemRegImmS7(const MachineInstr *MI, unsigned OpNo)
{
- char value = MI->getOperand(OpNo).getImmedValue();
+ char value = MI->getOperand(OpNo).getImm();
O << (int) value;
O << "(";
printOperand(MI, OpNo+1);
@@ -127,19 +127,19 @@
void
printS16ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- O << (short) MI->getOperand(OpNo).getImmedValue();
+ O << (short) MI->getOperand(OpNo).getImm();
}
void
printU16ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
+ O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void
printU32ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- O << (unsigned)MI->getOperand(OpNo).getImmedValue();
+ O << (unsigned)MI->getOperand(OpNo).getImm();
}
void
@@ -156,7 +156,7 @@
void
printU18ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- unsigned int value = MI->getOperand(OpNo).getImmedValue();
+ unsigned int value = MI->getOperand(OpNo).getImm();
assert(value <= (1 << 19) - 1 && "Invalid u18 argument");
O << value;
}
@@ -164,7 +164,7 @@
void
printS10ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
+ short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
assert((value >= -(1 << 9) && value <= (1 << 9) - 1)
&& "Invalid s10 argument");
@@ -174,7 +174,7 @@
void
printU10ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
+ short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
assert((value <= (1 << 10) - 1) && "Invalid u10 argument");
O << value;
@@ -238,23 +238,23 @@
void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
- int value = (int) MI->getOperand(OpNo).getImmedValue();
+ int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 16)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
- int value = (int) MI->getOperand(OpNo).getImmedValue();
+ int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 32)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index cd0e8e2..0906bea 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -64,7 +64,7 @@
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
- if (MI.getOperand(2).getImmedValue() == 0) {
+ if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -77,7 +77,7 @@
(MI.getOperand(1).isRegister() ||
MI.getOperand(1).isFrameIndex()) &&
(MI.getOperand(2).isImmediate() &&
- MI.getOperand(2).getImmedValue() == 0)) {
+ MI.getOperand(2).getImm() == 0)) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -137,7 +137,7 @@
case SPU::LQXr64:
case SPU::LQXr32:
case SPU::LQXr16:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@@ -171,7 +171,7 @@
case SPU::STQXr32:
case SPU::STQXr16:
// case SPU::STQXr8:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 8a85e74..f344da2 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -263,11 +263,11 @@
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
- MIB.addReg(MO.getReg());
+ MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
- MIB.addFrameIndex(MO.getFrameIndex());
+ MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
}
@@ -349,11 +349,11 @@
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
- MIB.addReg(MO.getReg());
+ MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
- MIB.addFrameIndex(MO.getFrameIndex());
+ MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
}
@@ -610,10 +610,9 @@
MachineOperand &MO = MI.getOperand(OpNo);
// Offset is biased by $lr's slot at the bottom.
- Offset += MO.getImmedValue() + MFI->getStackSize()
- + SPUFrameInfo::minStackSize();
+ Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
assert((Offset & 0xf) == 0
- && "16-byte alignment violated in SPURegisterInfo::eliminateFrameIndex");
+ && "16-byte alignment violated in eliminateFrameIndex");
// Replace the FrameIndex with base register with $sp (aka $r1)
SPOp.ChangeToRegister(SPU::R1, false);