Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.
This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td
index 8a202d4..64e5f25 100644
--- a/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/lib/Target/SystemZ/SystemZInstrFP.td
@@ -25,15 +25,15 @@
return N->isExactlyValue(-0.0);
}]>;
-let usesCustomDAGSchedInserter = 1 in {
+let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
"# SelectF32 PSEUDO",
[(set FP32:$dst,
- (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
+ (SystemZselect FP32:$src1, FP32:$src2, imm:$cc, PSW))]>;
def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
"# SelectF64 PSEUDO",
[(set FP64:$dst,
- (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
+ (SystemZselect FP64:$src1, FP64:$src2, imm:$cc, PSW))]>;
}
//===----------------------------------------------------------------------===//