Asserting here is to violent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23814 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index d0dc799..12ca95f 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -462,7 +462,9 @@
// Pattern fragment types will be resolved when they are inlined.
return MVT::isUnknown;
} else if (R->isSubClassOf("Register")) {
- assert(0 && "Explicit registers not handled here yet!\n");
+ //const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo();
+ // TODO: if a register appears in exactly one regclass, we could use that
+ // type info.
return MVT::isUnknown;
} else if (R->isSubClassOf("ValueType")) {
// Using a VTSDNode.