Added initial support for DEBUG_LABEL allowing debug specific labels to be
inserted in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index cc4144c..9ce9a3e 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -103,7 +103,6 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool and
// ExternalSymbols nodes into the appropriate instructions to
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index d63157f..fb3b204 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -74,7 +74,6 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
//IA64 has these, but they are not implemented
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index a98c275..31e2259 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -102,7 +102,6 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index abbe95a..de865db 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -252,7 +252,9 @@
bool doFinalization(Module &M);
void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesAll();
AU.addRequired<MachineDebugInfo>();
+ PPCAsmPrinter::getAnalysisUsage(AU);
}
};
@@ -418,6 +420,9 @@
/// method to print assembly for each instruction.
///
bool DarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+ // FIXME - is this the earliest this can be set.
+ DW.SetDebugInfo(&getAnalysis<MachineDebugInfo>());
+
SetupMachineFunction(MF);
O << "\n\n";
@@ -486,7 +491,6 @@
Mang->setUseQuotes(true);
// Emit initial debug information.
- DW.SetDebugInfo(getAnalysisToUpdate<MachineDebugInfo>());
DW.BeginModule();
return false;
}
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 01d8f07..8eb4ac3 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -94,8 +94,11 @@
// PowerPC does not have truncstore for i1.
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
- // PowerPC doesn't have line number support yet.
+ // Support label based line numbers.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ // FIXME - use subtarget debug flags
+ if (TM.getSubtarget<PPCSubtarget>().isDarwin())
+ setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 3d3424d..66b1bad 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -955,11 +955,14 @@
// DWARF Pseudo Instructions
//
-def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file,
- i32imm:$id),
- "; .loc $file, $line, $col\nLdebug_loc$id:",
+def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
+ "; .loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
- (i32 imm:$file), (i32 imm:$id))]>;
+ (i32 imm:$file))]>;
+
+def DWARF_LABEL : Pseudo<(ops i32imm:$id),
+ "\nLdebug_loc$id:",
+ [(dwarf_label (i32 imm:$id))]>;
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 6c93a26..b80430d 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -153,7 +153,6 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
}
diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index 6c93a26..b80430d 100644
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -153,7 +153,6 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
}
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 13cd40e..9b19ada 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -440,9 +440,12 @@
//===----------------------------------------------------------------------===//
// Dwarf support.
//
-def SDT_dwarf_loc : SDTypeProfile<0, 4,
- [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>]>;
-def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
+def SDT_dwarf_loc : SDTypeProfile<0, 3,
+ [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
+def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
+
+def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
+def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1811f62..304165e 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -130,7 +130,6 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
if (X86ScalarSSE) {
// Set up the FP register classes.