Add support for a pattern matching instruction selector. This is still in
the early implementation phases, so it is disabled by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile
index ff4ab7c..ee4cf8c 100644
--- a/lib/Target/X86/Makefile
+++ b/lib/Target/X86/Makefile
@@ -5,22 +5,25 @@
# Make sure that tblgen is run, first thing.
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc \
- X86GenInstrInfo.inc
+ X86GenInstrInfo.inc X86GenInstrSelector.inc
-X86GenRegisterNames.inc: X86.td X86RegisterInfo.td $(TBLGEN)
- $(TBLGEN) X86.td -gen-register-enums -o $@
+X86GenRegisterNames.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
+ $(TBLGEN) $< -gen-register-enums -o $@
-X86GenRegisterInfo.h.inc: X86.td X86RegisterInfo.td $(TBLGEN)
- $(TBLGEN) X86.td -gen-register-desc-header -o $@
+X86GenRegisterInfo.h.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
+ $(TBLGEN) $< -gen-register-desc-header -o $@
-X86GenRegisterInfo.inc: X86.td X86RegisterInfo.td $(TBLGEN)
- $(TBLGEN) X86.td -gen-register-desc -o $@
+X86GenRegisterInfo.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
+ $(TBLGEN) $< -gen-register-desc -o $@
-X86GenInstrNames.inc: X86.td X86InstrInfo.td $(TBLGEN)
- $(TBLGEN) X86.td -gen-instr-enums -o $@
+X86GenInstrNames.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
+ $(TBLGEN) $< -gen-instr-enums -o $@
-X86GenInstrInfo.inc: X86.td X86InstrInfo.td $(TBLGEN)
- $(TBLGEN) X86.td -gen-instr-desc -o $@
+X86GenInstrInfo.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
+ $(TBLGEN) $< -gen-instr-desc -o $@
+
+X86GenInstrSelector.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
+ $(TBLGEN) $< -gen-instr-selector -o $@
clean::
$(VERB) rm -f *.inc