Handle composed subreg indices when processing REQ_SEQUENCE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105066 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 3d10dc1..3f7a610 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1136,14 +1136,13 @@
static void UpdateRegSequenceSrcs(unsigned SrcReg,
unsigned DstReg, unsigned SubIdx,
- MachineRegisterInfo *MRI) {
+ MachineRegisterInfo *MRI,
+ const TargetRegisterInfo &TRI) {
for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
RE = MRI->reg_end(); RI != RE; ) {
MachineOperand &MO = RI.getOperand();
++RI;
- MO.setReg(DstReg);
- assert(MO.getSubReg() == 0);
- MO.setSubReg(SubIdx);
+ MO.substVirtReg(DstReg, SubIdx, TRI);
}
}
@@ -1315,7 +1314,7 @@
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
unsigned SrcReg = MI->getOperand(i).getReg();
unsigned SubIdx = MI->getOperand(i+1).getImm();
- UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI);
+ UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
}
if (IsImpDef) {