Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 32035b0..dd46bb4 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -87,7 +87,7 @@
// store [4096 x i8] %data, [4096 x i8]* %buffer
static const unsigned MaxParallelChains = 64;
-static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
+static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
const SDValue *Parts, unsigned NumParts,
MVT PartVT, EVT ValueVT, const Value *V);
@@ -96,7 +96,7 @@
/// larger then ValueVT then AssertOp can be used to specify whether the extra
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
/// (ISD::AssertSext).
-static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
+static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
const SDValue *Parts,
unsigned NumParts, MVT PartVT, EVT ValueVT,
const Value *V,
@@ -217,7 +217,7 @@
/// type larger then ValueVT then AssertOp can be used to specify whether the
/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
/// ValueVT (ISD::AssertSext).
-static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
+static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
const SDValue *Parts, unsigned NumParts,
MVT PartVT, EVT ValueVT, const Value *V) {
assert(ValueVT.isVector() && "Not a vector value");
@@ -327,14 +327,14 @@
return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
}
-static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
+static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
SDValue Val, SDValue *Parts, unsigned NumParts,
MVT PartVT, const Value *V);
/// getCopyToParts - Create a series of nodes that contain the specified value
/// split into legal parts. If the parts contain more bits than Val, then, for
/// integers, ExtendKind can be used to specify how to generate the extra bits.
-static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
+static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
SDValue Val, SDValue *Parts, unsigned NumParts,
MVT PartVT, const Value *V,
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
@@ -466,7 +466,7 @@
/// getCopyToPartsVector - Create a series of nodes that contain the specified
/// value split into legal parts.
-static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
+static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
SDValue Val, SDValue *Parts, unsigned NumParts,
MVT PartVT, const Value *V) {
EVT ValueVT = Val.getValueType();
@@ -644,7 +644,7 @@
/// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used.
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
- DebugLoc dl,
+ SDLoc dl,
SDValue &Chain, SDValue *Flag,
const Value *V = 0) const;
@@ -652,7 +652,7 @@
/// specified value into the registers specified by this object. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used.
- void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
+ void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
SDValue &Chain, SDValue *Flag, const Value *V) const;
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
@@ -671,7 +671,7 @@
/// If the Flag pointer is NULL, no flag is used.
SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
FunctionLoweringInfo &FuncInfo,
- DebugLoc dl,
+ SDLoc dl,
SDValue &Chain, SDValue *Flag,
const Value *V) const {
// A Value with type {} or [0 x %t] needs no registers.
@@ -761,7 +761,7 @@
/// specified value into the registers specified by this object. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used.
-void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
+void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
SDValue &Chain, SDValue *Flag,
const Value *V) const {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -900,7 +900,7 @@
}
// Otherwise, we have to make a token factor node.
- SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
&PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
@@ -930,7 +930,7 @@
PendingExports.push_back(Root);
}
- Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
&PendingExports[0],
PendingExports.size());
PendingExports.clear();
@@ -1022,7 +1022,7 @@
unsigned InReg = It->second;
RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
SDValue Chain = DAG.getEntryNode();
- N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
+ N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
resolveDanglingDebugInfo(V, N);
return N;
}
@@ -1058,7 +1058,7 @@
return DAG.getConstant(*CI, VT);
if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
- return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
+ return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
if (isa<ConstantPointerNull>(C))
return DAG.getConstant(0, TLI.getPointerTy());
@@ -1090,7 +1090,7 @@
}
return DAG.getMergeValues(&Constants[0], Constants.size(),
- getCurDebugLoc());
+ getCurSDLoc());
}
if (const ConstantDataSequential *CDS =
@@ -1105,8 +1105,8 @@
}
if (isa<ArrayType>(CDS->getType()))
- return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
- return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
+ return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
+ return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
VT, &Ops[0], Ops.size());
}
@@ -1131,7 +1131,7 @@
}
return DAG.getMergeValues(&Constants[0], NumElts,
- getCurDebugLoc());
+ getCurSDLoc());
}
if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
@@ -1159,7 +1159,7 @@
}
// Create a BUILD_VECTOR node.
- return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
+ return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
VT, &Ops[0], Ops.size());
}
@@ -1177,7 +1177,7 @@
unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
SDValue Chain = DAG.getEntryNode();
- return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
+ return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
}
llvm_unreachable("Can't get register for value!");
@@ -1209,17 +1209,17 @@
SmallVector<SDValue, 4> Chains(NumValues);
for (unsigned i = 0; i != NumValues; ++i) {
- SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
RetPtr.getValueType(), RetPtr,
DAG.getIntPtrConstant(Offsets[i]));
Chains[i] =
- DAG.getStore(Chain, getCurDebugLoc(),
+ DAG.getStore(Chain, getCurSDLoc(),
SDValue(RetOp.getNode(), RetOp.getResNo() + i),
// FIXME: better loc info would be nice.
Add, MachinePointerInfo(), false, false, 0);
}
- Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], NumValues);
} else if (I.getNumOperands() != 0) {
SmallVector<EVT, 4> ValueVTs;
@@ -1246,7 +1246,7 @@
unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
SmallVector<SDValue, 4> Parts(NumParts);
- getCopyToParts(DAG, getCurDebugLoc(),
+ getCopyToParts(DAG, getCurSDLoc(),
SDValue(RetOp.getNode(), RetOp.getResNo() + j),
&Parts[0], NumParts, PartVT, &I, ExtendKind);
@@ -1275,7 +1275,7 @@
CallingConv::ID CallConv =
DAG.getMachineFunction().getFunction()->getCallingConv();
Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
- Outs, OutVals, getCurDebugLoc(), DAG);
+ Outs, OutVals, getCurSDLoc(), DAG);
// Verify that the target's LowerReturn behaved as expected.
assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
@@ -1519,7 +1519,7 @@
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
MVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
@@ -1596,7 +1596,7 @@
MachineBasicBlock *SwitchBB) {
SDValue Cond;
SDValue CondLHS = getValue(CB.CmpLHS);
- DebugLoc dl = getCurDebugLoc();
+ SDLoc dl = getCurSDLoc();
// Build the setcc now.
if (CB.CmpMHS == NULL) {
@@ -1672,10 +1672,10 @@
// Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!");
EVT PTy = TLI.getPointerTy();
- SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
+ SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
- SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
+ SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
MVT::Other, Index.getValue(1),
Table, Index);
DAG.setRoot(BrJumpTable);
@@ -1691,7 +1691,7 @@
// difference between smallest and largest cases.
SDValue SwitchOp = getValue(JTH.SValue);
EVT VT = SwitchOp.getValueType();
- SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
+ SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
DAG.getConstant(JTH.First, VT));
// The SDNode we just created, which holds the value being switched on minus
@@ -1699,17 +1699,17 @@
// can be used as an index into the jump table in a subsequent basic block.
// This value may be smaller or larger than the target's pointer type, and
// therefore require extension or truncating.
- SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
+ SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
- SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
+ SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
JumpTableReg, SwitchOp);
JT.Reg = JumpTableReg;
// Emit the range check for the jump table, and branch to the default block
// for the switch statement if the value being switched on exceeds the largest
// case in the switch.
- SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
+ SDValue CMP = DAG.getSetCC(getCurSDLoc(),
TLI.getSetCCResultType(*DAG.getContext(),
Sub.getValueType()),
Sub,
@@ -1724,12 +1724,12 @@
if (++BBI != FuncInfo.MF->end())
NextBlock = BBI;
- SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
+ SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
MVT::Other, CopyTo, CMP,
DAG.getBasicBlock(JT.Default));
if (JT.MBB != NextBlock)
- BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
+ BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
DAG.getBasicBlock(JT.MBB));
DAG.setRoot(BrCond);
@@ -1742,11 +1742,11 @@
// Subtract the minimum value
SDValue SwitchOp = getValue(B.SValue);
EVT VT = SwitchOp.getValueType();
- SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
+ SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
DAG.getConstant(B.First, VT));
// Check range
- SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
+ SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
TLI.getSetCCResultType(*DAG.getContext(),
Sub.getValueType()),
Sub, DAG.getConstant(B.Range, VT),
@@ -1767,12 +1767,12 @@
}
if (UsePtrType) {
VT = TLI.getPointerTy();
- Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
+ Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
}
B.RegVT = VT.getSimpleVT();
B.Reg = FuncInfo.CreateReg(B.RegVT);
- SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
+ SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
B.Reg, Sub);
// Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1787,12 +1787,12 @@
addSuccessorWithWeight(SwitchBB, B.Default);
addSuccessorWithWeight(SwitchBB, MBB);
- SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
+ SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
MVT::Other, CopyTo, RangeCmp,
DAG.getBasicBlock(B.Default));
if (MBB != NextBlock)
- BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
+ BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
DAG.getBasicBlock(MBB));
DAG.setRoot(BrRange);
@@ -1806,34 +1806,34 @@
BitTestCase &B,
MachineBasicBlock *SwitchBB) {
MVT VT = BB.RegVT;
- SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
+ SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
Reg, VT);
SDValue Cmp;
unsigned PopCount = CountPopulation_64(B.Mask);
if (PopCount == 1) {
// Testing for a single bit; just compare the shift count with what it
// would need to be to shift a 1 bit in that position.
- Cmp = DAG.getSetCC(getCurDebugLoc(),
+ Cmp = DAG.getSetCC(getCurSDLoc(),
TLI.getSetCCResultType(*DAG.getContext(), VT),
ShiftOp,
DAG.getConstant(countTrailingZeros(B.Mask), VT),
ISD::SETEQ);
} else if (PopCount == BB.Range) {
// There is only one zero bit in the range, test for it directly.
- Cmp = DAG.getSetCC(getCurDebugLoc(),
+ Cmp = DAG.getSetCC(getCurSDLoc(),
TLI.getSetCCResultType(*DAG.getContext(), VT),
ShiftOp,
DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
ISD::SETNE);
} else {
// Make desired shift
- SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
+ SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
DAG.getConstant(1, VT), ShiftOp);
// Emit bit tests and jumps
- SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
+ SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
VT, SwitchVal, DAG.getConstant(B.Mask, VT));
- Cmp = DAG.getSetCC(getCurDebugLoc(),
+ Cmp = DAG.getSetCC(getCurSDLoc(),
TLI.getSetCCResultType(*DAG.getContext(), VT),
AndOp, DAG.getConstant(0, VT),
ISD::SETNE);
@@ -1844,7 +1844,7 @@
// The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
- SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
+ SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
MVT::Other, getControlRoot(),
Cmp, DAG.getBasicBlock(B.TargetBB));
@@ -1856,7 +1856,7 @@
NextBlock = BBI;
if (NextMBB != NextBlock)
- BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
+ BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
DAG.getBasicBlock(NextMBB));
DAG.setRoot(BrAnd);
@@ -1888,7 +1888,7 @@
addSuccessorWithWeight(InvokeMBB, LandingPad);
// Drop into normal successor.
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
MVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
@@ -1920,20 +1920,20 @@
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDValue Ops[2];
Ops[0] = DAG.getRoot();
- SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
+ SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurSDLoc(), VTs, Ops, 1);
SDValue Chain = Op1.getValue(1);
// Insert the EHSELECTION instruction.
VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
Ops[0] = Op1;
Ops[1] = Chain;
- SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
+ SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurSDLoc(), VTs, Ops, 2);
Chain = Op2.getValue(1);
- Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
+ Op2 = DAG.getSExtOrTrunc(Op2, getCurSDLoc(), MVT::i32);
Ops[0] = Op1;
Ops[1] = Op2;
- SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
&Ops[0], 2);
@@ -1990,7 +1990,7 @@
SDValue CondLHS = getValue(SV);
EVT VT = CondLHS.getValueType();
- DebugLoc DL = getCurDebugLoc();
+ SDLoc DL = getCurSDLoc();
SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
DAG.getConstant(CommonBit, VT));
@@ -2560,7 +2560,7 @@
// If this is not a fall-through branch, emit the branch.
SwitchMBB->addSuccessor(Default);
if (Default != NextBlock)
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
MVT::Other, getControlRoot(),
DAG.getBasicBlock(Default)));
@@ -2627,7 +2627,7 @@
addSuccessorWithWeight(IndirectBrMBB, Succ);
}
- DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
MVT::Other, getControlRoot(),
getValue(I.getAddress())));
}
@@ -2638,7 +2638,7 @@
if (isa<Constant>(I.getOperand(0)) &&
I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
SDValue Op2 = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
Op2.getValueType(), Op2));
return;
}
@@ -2649,7 +2649,7 @@
void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
Op1.getValueType(), Op1, Op2));
}
@@ -2663,7 +2663,7 @@
if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
unsigned ShiftSize = ShiftTy.getSizeInBits();
unsigned Op2Size = Op2.getValueType().getSizeInBits();
- DebugLoc DL = getCurDebugLoc();
+ SDLoc DL = getCurSDLoc();
// If the operand is smaller than the shift count type, promote it.
if (ShiftSize > Op2Size)
@@ -2681,7 +2681,7 @@
Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
}
- setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
Op1.getValueType(), Op1, Op2));
}
@@ -2695,9 +2695,9 @@
if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
!isa<ConstantSDNode>(Op1) &&
isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
- setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
+ setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
else
- setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
+ setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
Op1, Op2));
}
@@ -2712,7 +2712,7 @@
ISD::CondCode Opcode = getICmpCondCode(predicate);
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
+ setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
}
void SelectionDAGBuilder::visitFCmp(const User &I) {
@@ -2727,7 +2727,7 @@
if (TM.Options.NoNaNsFPMath)
Condition = getFCmpCodeWithoutNaN(Condition);
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
+ setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
}
void SelectionDAGBuilder::visitSelect(const User &I) {
@@ -2744,7 +2744,7 @@
ISD::VSELECT : ISD::SELECT;
for (unsigned i = 0; i != NumValues; ++i)
- Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
+ Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
Cond,
SDValue(TrueVal.getNode(),
@@ -2752,7 +2752,7 @@
SDValue(FalseVal.getNode(),
FalseVal.getResNo() + i));
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(&ValueVTs[0], NumValues),
&Values[0], NumValues));
}
@@ -2761,7 +2761,7 @@
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitZExt(const User &I) {
@@ -2769,7 +2769,7 @@
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitSExt(const User &I) {
@@ -2777,14 +2777,14 @@
// SExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitFPTrunc(const User &I) {
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
DestVT, N,
DAG.getTargetConstant(0, TLI.getPointerTy())));
}
@@ -2793,35 +2793,35 @@
// FPExt is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitFPToUI(const User &I) {
// FPToUI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitFPToSI(const User &I) {
// FPToSI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitUIToFP(const User &I) {
// UIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitSIToFP(const User &I){
// SIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
+ setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitPtrToInt(const User &I) {
@@ -2829,7 +2829,7 @@
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
+ setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
}
void SelectionDAGBuilder::visitIntToPtr(const User &I) {
@@ -2837,7 +2837,7 @@
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
+ setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
}
void SelectionDAGBuilder::visitBitCast(const User &I) {
@@ -2847,7 +2847,7 @@
// BitCast assures us that source and destination are the same size so this is
// either a BITCAST or a no-op.
if (DestVT != N.getValueType())
- setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
DestVT, N)); // convert types.
else
setValue(&I, N); // noop cast.
@@ -2856,20 +2856,20 @@
void SelectionDAGBuilder::visitInsertElement(const User &I) {
SDValue InVec = getValue(I.getOperand(0));
SDValue InVal = getValue(I.getOperand(1));
- SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
TLI.getPointerTy(),
getValue(I.getOperand(2)));
- setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
TLI.getValueType(I.getType()),
InVec, InVal, InIdx));
}
void SelectionDAGBuilder::visitExtractElement(const User &I) {
SDValue InVec = getValue(I.getOperand(0));
- SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
TLI.getPointerTy(),
getValue(I.getOperand(1)));
- setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
TLI.getValueType(I.getType()), InVec, InIdx));
}
@@ -2897,7 +2897,7 @@
unsigned SrcNumElts = SrcVT.getVectorNumElements();
if (SrcNumElts == MaskNumElts) {
- setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
+ setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
&Mask[0]));
return;
}
@@ -2912,7 +2912,7 @@
if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
// The shuffle is concatenating two vectors together.
- setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
VT, Src1, Src2));
return;
}
@@ -2920,7 +2920,7 @@
if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
// The shuffle is concatenating two vectors together.
- setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
VT, Src2, Src1));
return;
}
@@ -2938,10 +2938,10 @@
MOps2[0] = Src2;
Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
- getCurDebugLoc(), VT,
+ getCurSDLoc(), VT,
&MOps1[0], NumConcat);
Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
- getCurDebugLoc(), VT,
+ getCurSDLoc(), VT,
&MOps2[0], NumConcat);
// Readjust mask for new input vector length.
@@ -2953,7 +2953,7 @@
MappedOps.push_back(Idx);
}
- setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
+ setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
&MappedOps[0]));
return;
}
@@ -3013,7 +3013,7 @@
if (RangeUse[Input] == 0)
Src = DAG.getUNDEF(VT);
else
- Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
+ Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
Src, DAG.getIntPtrConstant(StartIdx[Input]));
}
@@ -3030,7 +3030,7 @@
MappedOps.push_back(Idx);
}
- setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
+ setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
&MappedOps[0]));
return;
}
@@ -3052,14 +3052,14 @@
SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
- Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
+ Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
EltVT, Src, DAG.getConstant(Idx, PtrVT));
}
Ops.push_back(Res);
}
- setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
VT, &Ops[0], Ops.size()));
}
@@ -3100,7 +3100,7 @@
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(&AggValueVTs[0], NumAggValues),
&Values[0], NumAggValues));
}
@@ -3134,7 +3134,7 @@
DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(&ValValueVTs[0], NumValValues),
&Values[0], NumValValues));
}
@@ -3153,7 +3153,7 @@
if (Field) {
// N = N + Offset
uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
- N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
+ N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
DAG.getConstant(Offset, N.getValueType()));
}
@@ -3170,13 +3170,13 @@
EVT PTy = TLI.getPointerTy();
unsigned PtrBits = PTy.getSizeInBits();
if (PtrBits < 64)
- OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
+ OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(),
TLI.getPointerTy(),
DAG.getConstant(Offs, MVT::i64));
else
OffsVal = DAG.getIntPtrConstant(Offs);
- N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
+ N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
OffsVal);
continue;
}
@@ -3188,24 +3188,24 @@
// If the index is smaller or larger than intptr_t, truncate or extend
// it.
- IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
+ IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
// If this is a multiply by a power of two, turn it into a shl
// immediately. This is a very common case.
if (ElementSize != 1) {
if (ElementSize.isPowerOf2()) {
unsigned Amt = ElementSize.logBase2();
- IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
+ IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
N.getValueType(), IdxN,
DAG.getConstant(Amt, IdxN.getValueType()));
} else {
SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
- IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
+ IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
N.getValueType(), IdxN, Scale);
}
}
- N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ N = DAG.getNode(ISD::ADD, getCurSDLoc(),
N.getValueType(), N, IdxN);
}
}
@@ -3229,9 +3229,9 @@
EVT IntPtr = TLI.getPointerTy();
if (AllocSize.getValueType() != IntPtr)
- AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
+ AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
- AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
+ AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
AllocSize,
DAG.getConstant(TySize, IntPtr));
@@ -3244,18 +3244,18 @@
// Round the size of the allocation up to the stack alignment size
// by add SA-1 to the size.
- AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
AllocSize.getValueType(), AllocSize,
DAG.getIntPtrConstant(StackAlign-1));
// Mask out the low bits for alignment purposes.
- AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
+ AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
AllocSize.getValueType(), AllocSize,
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
- SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
+ SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
VTs, Ops, 3);
setValue(&I, DSA);
DAG.setRoot(DSA.getValue(1));
@@ -3317,15 +3317,15 @@
// (MaxParallelChains should always remain as failsafe).
if (ChainI == MaxParallelChains) {
assert(PendingLoads.empty() && "PendingLoads must be serialized first");
- SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], ChainI);
Root = Chain;
ChainI = 0;
}
- SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT));
- SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
+ SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
isNonTemporal, isInvariant, Alignment, TBAAInfo,
Ranges);
@@ -3335,7 +3335,7 @@
}
if (!ConstantMemory) {
- SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], ChainI);
if (isVolatile)
DAG.setRoot(Chain);
@@ -3343,7 +3343,7 @@
PendingLoads.push_back(Chain);
}
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(&ValueVTs[0], NumValues),
&Values[0], NumValues));
}
@@ -3381,21 +3381,21 @@
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
// See visitLoad comments.
if (ChainI == MaxParallelChains) {
- SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], ChainI);
Root = Chain;
ChainI = 0;
}
- SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
+ SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT));
- SDValue St = DAG.getStore(Root, getCurDebugLoc(),
+ SDValue St = DAG.getStore(Root, getCurSDLoc(),
SDValue(Src.getNode(), Src.getResNo() + i),
Add, MachinePointerInfo(PtrV, Offsets[i]),
isVolatile, isNonTemporal, Alignment, TBAAInfo);
Chains[ChainI] = St;
}
- SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], ChainI);
++SDNodeOrder;
AssignOrderingToNode(StoreNode.getNode());
@@ -3404,7 +3404,7 @@
static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
SynchronizationScope Scope,
- bool Before, DebugLoc dl,
+ bool Before, SDLoc dl,
SelectionDAG &DAG,
const TargetLowering &TLI) {
// Fence, if necessary
@@ -3427,7 +3427,7 @@
}
void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
- DebugLoc dl = getCurDebugLoc();
+ SDLoc dl = getCurSDLoc();
AtomicOrdering Order = I.getOrdering();
SynchronizationScope Scope = I.getSynchScope();
@@ -3459,7 +3459,7 @@
}
void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
- DebugLoc dl = getCurDebugLoc();
+ SDLoc dl = getCurSDLoc();
ISD::NodeType NT;
switch (I.getOperation()) {
default: llvm_unreachable("Unknown atomicrmw operation");
@@ -3505,7 +3505,7 @@
}
void SelectionDAGBuilder::visitFence(const FenceInst &I) {
- DebugLoc dl = getCurDebugLoc();
+ SDLoc dl = getCurSDLoc();
SDValue Ops[3];
Ops[0] = getRoot();
Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
@@ -3514,7 +3514,7 @@
}
void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
- DebugLoc dl = getCurDebugLoc();
+ SDLoc dl = getCurSDLoc();
AtomicOrdering Order = I.getOrdering();
SynchronizationScope Scope = I.getSynchScope();
@@ -3543,7 +3543,7 @@
}
void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
- DebugLoc dl = getCurDebugLoc();
+ SDLoc dl = getCurSDLoc();
AtomicOrdering Order = I.getOrdering();
SynchronizationScope Scope = I.getSynchScope();
@@ -3620,20 +3620,20 @@
SDValue Result;
if (IsTgtIntrinsic) {
// This is target intrinsic that touches memory
- Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
+ Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
VTs, &Ops[0], Ops.size(),
Info.memVT,
MachinePointerInfo(Info.ptrVal, Info.offset),
Info.align, Info.vol,
Info.readMem, Info.writeMem);
} else if (!HasChain) {
- Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
+ Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
VTs, &Ops[0], Ops.size());
} else if (!I.getType()->isVoidTy()) {
- Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
+ Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
VTs, &Ops[0], Ops.size());
} else {
- Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
+ Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
VTs, &Ops[0], Ops.size());
}
@@ -3648,7 +3648,7 @@
if (!I.getType()->isVoidTy()) {
if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
EVT VT = TLI.getValueType(PTy);
- Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
+ Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
}
setValue(&I, Result);
@@ -3668,7 +3668,7 @@
///
/// where Op is the hexadecimal representation of floating point value.
static SDValue
-GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
+GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
DAG.getConstant(0x007fffff, MVT::i32));
SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
@@ -3683,7 +3683,7 @@
/// where Op is the hexadecimal representation of floating point value.
static SDValue
GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
- DebugLoc dl) {
+ SDLoc dl) {
SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
DAG.getConstant(0x7f800000, MVT::i32));
SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
@@ -3702,7 +3702,7 @@
/// expandExp - Lower an exp intrinsic. Handles the special sequences for
/// limited-precision mode.
-static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
+static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
if (Op.getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
@@ -3805,7 +3805,7 @@
/// expandLog - Lower a log intrinsic. Handles the special sequences for
/// limited-precision mode.
-static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
+static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
if (Op.getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
@@ -3901,7 +3901,7 @@
/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
/// limited-precision mode.
-static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
+static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
if (Op.getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
@@ -3996,7 +3996,7 @@
/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
/// limited-precision mode.
-static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
+static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
if (Op.getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
@@ -4084,7 +4084,7 @@
/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
/// limited-precision mode.
-static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
+static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
if (Op.getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
@@ -4179,7 +4179,7 @@
/// visitPow - Lower a pow intrinsic. Handles the special sequences for
/// limited-precision mode with x == 10.0f.
-static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS,
+static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
SelectionDAG &DAG, const TargetLowering &TLI) {
bool IsExp10 = false;
if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
@@ -4287,7 +4287,7 @@
/// ExpandPowI - Expand a llvm.powi intrinsic.
-static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
+static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
SelectionDAG &DAG) {
// If RHS is a constant, we can expand this out to a multiplication tree,
// otherwise we end up lowering to a call to __powidf2 (for example). When
@@ -4435,6 +4435,7 @@
/// otherwise lower it and return null.
const char *
SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
+ SDLoc sdl = getCurSDLoc();
DebugLoc dl = getCurDebugLoc();
SDValue Res;
@@ -4447,11 +4448,11 @@
case Intrinsic::vaend: visitVAEnd(I); return 0;
case Intrinsic::vacopy: visitVACopy(I); return 0;
case Intrinsic::returnaddress:
- setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
+ setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
getValue(I.getArgOperand(0))));
return 0;
case Intrinsic::frameaddress:
- setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
+ setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
getValue(I.getArgOperand(0))));
return 0;
case Intrinsic::setjmp:
@@ -4473,7 +4474,7 @@
if (!Align)
Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
- DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
+ DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
MachinePointerInfo(I.getArgOperand(0)),
MachinePointerInfo(I.getArgOperand(1))));
return 0;
@@ -4491,7 +4492,7 @@
if (!Align)
Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
- DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
+ DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
MachinePointerInfo(I.getArgOperand(0))));
return 0;
}
@@ -4510,7 +4511,7 @@
if (!Align)
Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
- DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
+ DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
MachinePointerInfo(I.getArgOperand(0)),
MachinePointerInfo(I.getArgOperand(1))));
return 0;
@@ -4677,7 +4678,7 @@
case Intrinsic::eh_return_i32:
case Intrinsic::eh_return_i64:
DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
- DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
+ DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
MVT::Other,
getControlRoot(),
getValue(I.getArgOperand(0)),
@@ -4687,17 +4688,17 @@
DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
return 0;
case Intrinsic::eh_dwarf_cfa: {
- SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
+ SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
TLI.getPointerTy());
- SDValue Offset = DAG.getNode(ISD::ADD, dl,
+ SDValue Offset = DAG.getNode(ISD::ADD, sdl,
TLI.getPointerTy(),
- DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
+ DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
TLI.getPointerTy()),
CfaArg);
- SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
+ SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
TLI.getPointerTy(),
DAG.getConstant(0, TLI.getPointerTy()));
- setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
+ setValue(&I, DAG.getNode(ISD::ADD, sdl, TLI.getPointerTy(),
FA, Offset));
return 0;
}
@@ -4723,7 +4724,7 @@
SDValue Ops[2];
Ops[0] = getRoot();
Ops[1] = getValue(I.getArgOperand(0));
- SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
+ SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
DAG.getVTList(MVT::i32, MVT::Other),
Ops, 2);
setValue(&I, Op.getValue(0));
@@ -4731,7 +4732,7 @@
return 0;
}
case Intrinsic::eh_sjlj_longjmp: {
- DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
+ DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
getRoot(), getValue(I.getArgOperand(0))));
return 0;
}
@@ -4786,10 +4787,10 @@
SDValue ShOps[2];
ShOps[0] = ShAmt;
ShOps[1] = DAG.getConstant(0, MVT::i32);
- ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
+ ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
EVT DestVT = TLI.getValueType(I.getType());
- ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
- Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
+ ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
+ Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
DAG.getConstant(NewIntrinsic, MVT::i32),
getValue(I.getArgOperand(0)), ShAmt);
setValue(&I, Res);
@@ -4803,7 +4804,7 @@
EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
ElVT.getVectorNumElements();
- Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
+ Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)),
DAG.getIntPtrConstant(Idx));
@@ -4817,7 +4818,7 @@
EVT DestVT = TLI.getValueType(I.getType());
uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
DestVT.getVectorNumElements();
- Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
+ Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
getValue(I.getArgOperand(0)),
DAG.getIntPtrConstant(Idx));
setValue(&I, Res);
@@ -4847,7 +4848,7 @@
}
EVT DestVT = TLI.getValueType(I.getType());
const Value *Op1 = I.getArgOperand(0);
- Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1),
+ Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
DAG.getValueType(DestVT),
DAG.getValueType(getValue(Op1).getValueType()),
getValue(I.getArgOperand(1)),
@@ -4857,26 +4858,26 @@
return 0;
}
case Intrinsic::powi:
- setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
+ setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)), DAG));
return 0;
case Intrinsic::log:
- setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI));
+ setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
return 0;
case Intrinsic::log2:
- setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
+ setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
return 0;
case Intrinsic::log10:
- setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI));
+ setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
return 0;
case Intrinsic::exp:
- setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI));
+ setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
return 0;
case Intrinsic::exp2:
- setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
+ setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
return 0;
case Intrinsic::pow:
- setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)),
+ setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)), DAG, TLI));
return 0;
case Intrinsic::sqrt:
@@ -4902,13 +4903,13 @@
case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
}
- setValue(&I, DAG.getNode(Opcode, dl,
+ setValue(&I, DAG.getNode(Opcode, sdl,
getValue(I.getArgOperand(0)).getValueType(),
getValue(I.getArgOperand(0))));
return 0;
}
case Intrinsic::fma:
- setValue(&I, DAG.getNode(ISD::FMA, dl,
+ setValue(&I, DAG.getNode(ISD::FMA, sdl,
getValue(I.getArgOperand(0)).getValueType(),
getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)),
@@ -4918,17 +4919,17 @@
EVT VT = TLI.getValueType(I.getType());
if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
TLI.isFMAFasterThanMulAndAdd(VT)){
- setValue(&I, DAG.getNode(ISD::FMA, dl,
+ setValue(&I, DAG.getNode(ISD::FMA, sdl,
getValue(I.getArgOperand(0)).getValueType(),
getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)),
getValue(I.getArgOperand(2))));
} else {
- SDValue Mul = DAG.getNode(ISD::FMUL, dl,
+ SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
getValue(I.getArgOperand(0)).getValueType(),
getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)));
- SDValue Add = DAG.getNode(ISD::FADD, dl,
+ SDValue Add = DAG.getNode(ISD::FADD, sdl,
getValue(I.getArgOperand(0)).getValueType(),
Mul,
getValue(I.getArgOperand(2)));
@@ -4937,21 +4938,21 @@
return 0;
}
case Intrinsic::convert_to_fp16:
- setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
+ setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
MVT::i16, getValue(I.getArgOperand(0))));
return 0;
case Intrinsic::convert_from_fp16:
- setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
+ setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
MVT::f32, getValue(I.getArgOperand(0))));
return 0;
case Intrinsic::pcmarker: {
SDValue Tmp = getValue(I.getArgOperand(0));
- DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
SDValue Op = getRoot();
- Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
+ Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
DAG.getVTList(MVT::i64, MVT::Other),
&Op, 1);
setValue(&I, Res);
@@ -4959,7 +4960,7 @@
return 0;
}
case Intrinsic::bswap:
- setValue(&I, DAG.getNode(ISD::BSWAP, dl,
+ setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
getValue(I.getArgOperand(0)).getValueType(),
getValue(I.getArgOperand(0))));
return 0;
@@ -4968,7 +4969,7 @@
ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
EVT Ty = Arg.getValueType();
setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
- dl, Ty, Arg));
+ sdl, Ty, Arg));
return 0;
}
case Intrinsic::ctlz: {
@@ -4976,18 +4977,18 @@
ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
EVT Ty = Arg.getValueType();
setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
- dl, Ty, Arg));
+ sdl, Ty, Arg));
return 0;
}
case Intrinsic::ctpop: {
SDValue Arg = getValue(I.getArgOperand(0));
EVT Ty = Arg.getValueType();
- setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
+ setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
return 0;
}
case Intrinsic::stacksave: {
SDValue Op = getRoot();
- Res = DAG.getNode(ISD::STACKSAVE, dl,
+ Res = DAG.getNode(ISD::STACKSAVE, sdl,
DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
setValue(&I, Res);
DAG.setRoot(Res.getValue(1));
@@ -4995,7 +4996,7 @@
}
case Intrinsic::stackrestore: {
Res = getValue(I.getArgOperand(0));
- DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
+ DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
return 0;
}
case Intrinsic::stackprotector: {
@@ -5013,7 +5014,7 @@
SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
// Store the stack protector onto the stack.
- Res = DAG.getStore(getRoot(), dl, Src, FIN,
+ Res = DAG.getStore(getRoot(), sdl, Src, FIN,
MachinePointerInfo::getFixedStack(FI),
true, false, 0);
setValue(&I, Res);
@@ -5057,13 +5058,13 @@
Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
Ops[5] = DAG.getSrcValue(F);
- Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
+ Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
DAG.setRoot(Res);
return 0;
}
case Intrinsic::adjust_trampoline: {
- setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
+ setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
TLI.getPointerTy(),
getValue(I.getArgOperand(0))));
return 0;
@@ -5081,7 +5082,7 @@
case Intrinsic::gcwrite:
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
case Intrinsic::flt_rounds:
- setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
+ setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
return 0;
case Intrinsic::expect: {
@@ -5096,7 +5097,7 @@
if (TrapFuncName.empty()) {
ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
ISD::TRAP : ISD::DEBUGTRAP;
- DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot()));
+ DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
return 0;
}
TargetLowering::ArgListTy Args;
@@ -5106,7 +5107,7 @@
/*isTailCall=*/false,
/*doesNotRet=*/false, /*isReturnValueUsed=*/true,
DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
- Args, DAG, dl);
+ Args, DAG, sdl);
std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
DAG.setRoot(Result.second);
return 0;
@@ -5132,7 +5133,7 @@
SDValue Op2 = getValue(I.getArgOperand(1));
SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
- setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2));
+ setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
return 0;
}
case Intrinsic::prefetch: {
@@ -5143,7 +5144,7 @@
Ops[2] = getValue(I.getArgOperand(1));
Ops[3] = getValue(I.getArgOperand(2));
Ops[4] = getValue(I.getArgOperand(3));
- DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
+ DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
DAG.getVTList(MVT::Other),
&Ops[0], 5,
EVT::getIntegerVT(*Context, 8),
@@ -5179,7 +5180,7 @@
Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
- Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2);
+ Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
DAG.setRoot(Res);
}
return 0;
@@ -5288,7 +5289,7 @@
// Both PendingLoads and PendingExports must be flushed here;
// this call might not return.
(void)getRoot();
- DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
+ DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
}
// Check if target-independent constraints permit a tail call here.
@@ -5298,7 +5299,7 @@
TargetLowering::
CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
- getCurDebugLoc(), CS);
+ getCurSDLoc(), CS);
std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
assert((isTailCall || Result.second.getNode()) &&
"Non-null chain expected with non-tail call!");
@@ -5326,22 +5327,22 @@
SmallVector<SDValue, 4> Chains(NumValues);
for (unsigned i = 0; i < NumValues; ++i) {
- SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
+ SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
DemoteStackSlot,
DAG.getConstant(Offsets[i], PtrVT));
- SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
+ SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
false, false, false, 1);
Values[i] = L;
Chains[i] = L.getValue(1);
}
- SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], NumValues);
PendingLoads.push_back(Chain);
setValue(CS.getInstruction(),
- DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(&RetTys[0], RetTys.size()),
&Values[0], Values.size()));
}
@@ -5364,7 +5365,7 @@
// Insert a label at the end of the invoke call to mark the try range. This
// can be used to detect deletion of the invoke via the MachineModuleInfo.
MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
- DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
+ DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
// Inform MachineModuleInfo of range.
MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
@@ -5419,7 +5420,7 @@
}
SDValue Ptr = Builder.getValue(PtrVal);
- SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
+ SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
Ptr, MachinePointerInfo(PtrVal),
false /*volatile*/,
false /*nontemporal*/,
@@ -5498,10 +5499,10 @@
SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
- SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
+ SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
ISD::SETNE);
EVT CallVT = TLI.getValueType(I.getType(), true);
- setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
+ setValue(&I, DAG.getZExtOrTrunc(Res, getCurSDLoc(), CallVT));
return true;
}
}
@@ -5523,7 +5524,7 @@
return false;
SDValue Tmp = getValue(I.getArgOperand(0));
- setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp));
+ setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
return true;
}
@@ -5572,7 +5573,7 @@
I.onlyReadsMemory()) {
SDValue LHS = getValue(I.getArgOperand(0));
SDValue RHS = getValue(I.getArgOperand(1));
- setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
LHS.getValueType(), LHS, RHS));
return;
}
@@ -5744,7 +5745,7 @@
///
static void GetRegistersForValue(SelectionDAG &DAG,
const TargetLowering &TLI,
- DebugLoc DL,
+ SDLoc DL,
SDISelAsmOperandInfo &OpInfo) {
LLVMContext &Context = *DAG.getContext();
@@ -5999,7 +6000,7 @@
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
- Chain = DAG.getStore(Chain, getCurDebugLoc(),
+ Chain = DAG.getStore(Chain, getCurSDLoc(),
OpInfo.CallOperand, StackSlot,
MachinePointerInfo::getFixedStack(SSFI),
false, false, 0);
@@ -6016,7 +6017,7 @@
// If this constraint is for a specific register, allocate it before
// anything else.
if (OpInfo.ConstraintType == TargetLowering::C_Register)
- GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
+ GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
}
// Second pass - Loop over all of the operands, assigning virtual or physregs
@@ -6027,7 +6028,7 @@
// C_Register operands have already been allocated, Other/Memory don't need
// to be.
if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
- GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
+ GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
}
// AsmNodeOperands - The operands for the ISD::INLINEASM node.
@@ -6191,7 +6192,7 @@
}
}
// Use the produced MatchedRegs object to
- MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
+ MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
Chain, &Flag, CS.getInstruction());
MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
true, OpInfo.getMatchedOperand(),
@@ -6273,7 +6274,7 @@
break;
}
- OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
+ OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
Chain, &Flag, CS.getInstruction());
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
@@ -6296,7 +6297,7 @@
AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
- Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
+ Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
DAG.getVTList(MVT::Other, MVT::Glue),
&AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
@@ -6304,7 +6305,7 @@
// If this asm returns a register value, copy the result from that register
// and set it as the value of the call.
if (!RetValRegs.Regs.empty()) {
- SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
+ SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
Chain, &Flag, CS.getInstruction());
// FIXME: Why don't we do this for inline asms with MRVs?
@@ -6317,7 +6318,7 @@
// not have the same VT as was expected. Convert it to the right type
// with bit_convert.
if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
- Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
+ Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
ResultType, Val);
} else if (ResultType != Val.getValueType() &&
@@ -6325,7 +6326,7 @@
// If a result value was tied to an input value, the computed result may
// have a wider width than the expected result. Extract the relevant
// portion.
- Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
+ Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
}
assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
@@ -6344,7 +6345,7 @@
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
const Value *Ptr = IndirectStoresToEmit[i].second;
- SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
+ SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
Chain, &Flag, IA);
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
}
@@ -6352,7 +6353,7 @@
// Emit the non-flagged stores from the physregs.
SmallVector<SDValue, 8> OutChains;
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
- SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
+ SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
StoresToEmit[i].first,
getValue(StoresToEmit[i].second),
MachinePointerInfo(StoresToEmit[i].second),
@@ -6361,14 +6362,14 @@
}
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
&OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
- DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
MVT::Other, getRoot(),
getValue(I.getArgOperand(0)),
DAG.getSrcValue(I.getArgOperand(0))));
@@ -6376,7 +6377,7 @@
void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
const DataLayout &TD = *TLI.getDataLayout();
- SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
+ SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
getRoot(), getValue(I.getOperand(0)),
DAG.getSrcValue(I.getOperand(0)),
TD.getABITypeAlignment(I.getType()));
@@ -6385,14 +6386,14 @@
}
void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
- DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
MVT::Other, getRoot(),
getValue(I.getArgOperand(0)),
DAG.getSrcValue(I.getArgOperand(0))));
}
void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
- DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
MVT::Other, getRoot(),
getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)),
@@ -6601,7 +6602,7 @@
RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
SDValue Chain = DAG.getEntryNode();
- RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V);
+ RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
PendingExports.push_back(Chain);
}
@@ -6628,7 +6629,7 @@
void SelectionDAGISel::LowerArguments(const Function &F) {
SelectionDAG &DAG = SDB->DAG;
- DebugLoc dl = SDB->getCurDebugLoc();
+ SDLoc dl = SDB->getCurSDLoc();
const DataLayout *TD = TLI.getDataLayout();
SmallVector<ISD::InputArg, 16> Ins;
@@ -6743,7 +6744,7 @@
MachineRegisterInfo& RegInfo = MF.getRegInfo();
unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
FuncInfo->DemoteRegister = SRetReg;
- NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
+ NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
SRetReg, ArgValue);
DAG.setRoot(NewRoot);
@@ -6800,7 +6801,7 @@
FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
- SDB->getCurDebugLoc());
+ SDB->getCurSDLoc());
SDB->setValue(I, Res);
if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {