Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index 58959ed..1d8d7a7 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
@@ -425,9 +425,9 @@
O << '%';
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- MVT VT = (strcmp(Modifier+6,"64") == 0) ?
- MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
- ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
+ EVT VT = (strcmp(Modifier+6,"64") == 0) ?
+ EVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? EVT::i32 :
+ ((strcmp(Modifier+6,"16") == 0) ? EVT::i16 : EVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << TRI->getAsmName(Reg);
@@ -573,19 +573,19 @@
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i8);
+ Reg = getX86SubSuperRegister(Reg, EVT::i8);
break;
case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
+ Reg = getX86SubSuperRegister(Reg, EVT::i8, true);
break;
case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i16);
+ Reg = getX86SubSuperRegister(Reg, EVT::i16);
break;
case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i32);
+ Reg = getX86SubSuperRegister(Reg, EVT::i32);
break;
case 'q': // Print DImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i64);
+ Reg = getX86SubSuperRegister(Reg, EVT::i64);
break;
}
@@ -685,7 +685,7 @@
unsigned Reg = MI->getOperand(i).getReg();
if (Reg == 0) continue;
- MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
+ MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, EVT::i64));
}
}
diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
index 2324479..34908da 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
@@ -75,9 +75,9 @@
unsigned Reg = Op.getReg();
#if 0
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- MVT VT = (strcmp(Modifier+6,"64") == 0) ?
- MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
- ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
+ EVT VT = (strcmp(Modifier+6,"64") == 0) ?
+ EVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? EVT::i32 :
+ ((strcmp(Modifier+6,"16") == 0) ? EVT::i16 : EVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
#endif
diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
index c9a761d..08f5aa4 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
@@ -209,9 +209,9 @@
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- MVT VT = (strcmp(Modifier,"subreg64") == 0) ?
- MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
- ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
+ EVT VT = (strcmp(Modifier,"subreg64") == 0) ?
+ EVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? EVT::i32 :
+ ((strcmp(Modifier,"subreg16") == 0) ? EVT::i16 :EVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << TRI->getName(Reg);
@@ -376,16 +376,16 @@
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i8);
+ Reg = getX86SubSuperRegister(Reg, EVT::i8);
break;
case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
+ Reg = getX86SubSuperRegister(Reg, EVT::i8, true);
break;
case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i16);
+ Reg = getX86SubSuperRegister(Reg, EVT::i16);
break;
case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i32);
+ Reg = getX86SubSuperRegister(Reg, EVT::i32);
break;
}
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index a4bb1be..3046681 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -79,16 +79,16 @@
#include "X86GenFastISel.inc"
private:
- bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
+ bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT);
- bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
+ bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
- bool X86FastEmitStore(MVT VT, Value *Val,
+ bool X86FastEmitStore(EVT VT, Value *Val,
const X86AddressMode &AM);
- bool X86FastEmitStore(MVT VT, unsigned Val,
+ bool X86FastEmitStore(EVT VT, unsigned Val,
const X86AddressMode &AM);
- bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
+ bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
unsigned &ResultReg);
bool X86SelectAddress(Value *V, X86AddressMode &AM);
@@ -133,36 +133,36 @@
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
- bool isScalarFPTypeInSSEReg(MVT VT) const {
- return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
- (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
+ bool isScalarFPTypeInSSEReg(EVT VT) const {
+ return (VT == EVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
+ (VT == EVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
- bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
+ bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
};
} // end anonymous namespace.
-bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
+bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
- if (VT == MVT::Other || !VT.isSimple())
+ if (VT == EVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
// For now, require SSE/SSE2 for performing floating-point operations,
// since x87 requires additional work.
- if (VT == MVT::f64 && !X86ScalarSSEf64)
+ if (VT == EVT::f64 && !X86ScalarSSEf64)
return false;
- if (VT == MVT::f32 && !X86ScalarSSEf32)
+ if (VT == EVT::f32 && !X86ScalarSSEf32)
return false;
// Similarly, no f80 support yet.
- if (VT == MVT::f80)
+ if (VT == EVT::f80)
return false;
// We only handle legal types. For example, on x86-32 the instruction
// selector contains all of the 64-bit instructions from x86-64,
// under the assumption that i64 won't be used if the target doesn't
// support it.
- return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
+ return (AllowI1 && VT == EVT::i1) || TLI.isTypeLegal(VT);
}
#include "X86GenCallingConv.inc"
@@ -188,31 +188,31 @@
/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
/// Return true and the result register by reference if it is possible.
-bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
+bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
unsigned &ResultReg) {
// Get opcode and regclass of the output for the given load instruction.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
switch (VT.getSimpleVT()) {
default: return false;
- case MVT::i8:
+ case EVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
break;
- case MVT::i16:
+ case EVT::i16:
Opc = X86::MOV16rm;
RC = X86::GR16RegisterClass;
break;
- case MVT::i32:
+ case EVT::i32:
Opc = X86::MOV32rm;
RC = X86::GR32RegisterClass;
break;
- case MVT::i64:
+ case EVT::i64:
// Must be in x86-64 mode.
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
break;
- case MVT::f32:
+ case EVT::f32:
if (Subtarget->hasSSE1()) {
Opc = X86::MOVSSrm;
RC = X86::FR32RegisterClass;
@@ -221,7 +221,7 @@
RC = X86::RFP32RegisterClass;
}
break;
- case MVT::f64:
+ case EVT::f64:
if (Subtarget->hasSSE2()) {
Opc = X86::MOVSDrm;
RC = X86::FR64RegisterClass;
@@ -230,7 +230,7 @@
RC = X86::RFP64RegisterClass;
}
break;
- case MVT::f80:
+ case EVT::f80:
// No f80 support yet.
return false;
}
@@ -245,21 +245,21 @@
/// and a displacement offset, or a GlobalAddress,
/// i.e. V. Return true if it is possible.
bool
-X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
+X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
const X86AddressMode &AM) {
// Get opcode and regclass of the output for the given store instruction.
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
- case MVT::f80: // No f80 support yet.
+ case EVT::f80: // No f80 support yet.
default: return false;
- case MVT::i8: Opc = X86::MOV8mr; break;
- case MVT::i16: Opc = X86::MOV16mr; break;
- case MVT::i32: Opc = X86::MOV32mr; break;
- case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
- case MVT::f32:
+ case EVT::i8: Opc = X86::MOV8mr; break;
+ case EVT::i16: Opc = X86::MOV16mr; break;
+ case EVT::i32: Opc = X86::MOV32mr; break;
+ case EVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
+ case EVT::f32:
Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
break;
- case MVT::f64:
+ case EVT::f64:
Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
break;
}
@@ -268,7 +268,7 @@
return true;
}
-bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
+bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val,
const X86AddressMode &AM) {
// Handle 'null' like i32/i64 0.
if (isa<ConstantPointerNull>(Val))
@@ -279,10 +279,10 @@
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
default: break;
- case MVT::i8: Opc = X86::MOV8mi; break;
- case MVT::i16: Opc = X86::MOV16mi; break;
- case MVT::i32: Opc = X86::MOV32mi; break;
- case MVT::i64:
+ case EVT::i8: Opc = X86::MOV8mi; break;
+ case EVT::i16: Opc = X86::MOV16mi; break;
+ case EVT::i32: Opc = X86::MOV32mi; break;
+ case EVT::i64:
// Must be a 32-bit sign extended value.
if ((int)CI->getSExtValue() == CI->getSExtValue())
Opc = X86::MOV64mi32;
@@ -306,8 +306,8 @@
/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
/// ISD::SIGN_EXTEND).
-bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
- unsigned Src, MVT SrcVT,
+bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
+ unsigned Src, EVT SrcVT,
unsigned &ResultReg) {
unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
@@ -478,7 +478,7 @@
StubAM.GV = GV;
StubAM.GVOpFlags = GVFlags;
- if (TLI.getPointerTy() == MVT::i64) {
+ if (TLI.getPointerTy() == EVT::i64) {
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
@@ -605,7 +605,7 @@
/// X86SelectStore - Select and emit code to implement store instructions.
bool X86FastISel::X86SelectStore(Instruction* I) {
- MVT VT;
+ EVT VT;
if (!isTypeLegal(I->getOperand(0)->getType(), VT))
return false;
@@ -619,7 +619,7 @@
/// X86SelectLoad - Select and emit code to implement load instructions.
///
bool X86FastISel::X86SelectLoad(Instruction *I) {
- MVT VT;
+ EVT VT;
if (!isTypeLegal(I->getType(), VT))
return false;
@@ -635,29 +635,29 @@
return false;
}
-static unsigned X86ChooseCmpOpcode(MVT VT) {
+static unsigned X86ChooseCmpOpcode(EVT VT) {
switch (VT.getSimpleVT()) {
default: return 0;
- case MVT::i8: return X86::CMP8rr;
- case MVT::i16: return X86::CMP16rr;
- case MVT::i32: return X86::CMP32rr;
- case MVT::i64: return X86::CMP64rr;
- case MVT::f32: return X86::UCOMISSrr;
- case MVT::f64: return X86::UCOMISDrr;
+ case EVT::i8: return X86::CMP8rr;
+ case EVT::i16: return X86::CMP16rr;
+ case EVT::i32: return X86::CMP32rr;
+ case EVT::i64: return X86::CMP64rr;
+ case EVT::f32: return X86::UCOMISSrr;
+ case EVT::f64: return X86::UCOMISDrr;
}
}
/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
/// of the comparison, return an opcode that works for the compare (e.g.
/// CMP32ri) otherwise return 0.
-static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
+static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) {
switch (VT.getSimpleVT()) {
// Otherwise, we can't fold the immediate into this comparison.
default: return 0;
- case MVT::i8: return X86::CMP8ri;
- case MVT::i16: return X86::CMP16ri;
- case MVT::i32: return X86::CMP32ri;
- case MVT::i64:
+ case EVT::i8: return X86::CMP8ri;
+ case EVT::i16: return X86::CMP16ri;
+ case EVT::i32: return X86::CMP32ri;
+ case EVT::i64:
// 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
// field.
if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
@@ -666,7 +666,7 @@
}
}
-bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
+bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) {
unsigned Op0Reg = getRegForValue(Op0);
if (Op0Reg == 0) return false;
@@ -698,7 +698,7 @@
bool X86FastISel::X86SelectCmp(Instruction *I) {
CmpInst *CI = cast<CmpInst>(I);
- MVT VT;
+ EVT VT;
if (!isTypeLegal(I->getOperand(0)->getType(), VT))
return false;
@@ -778,7 +778,7 @@
unsigned ResultReg = getRegForValue(I->getOperand(0));
if (ResultReg == 0) return false;
// Set the high bits to zero.
- ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
+ ResultReg = FastEmitZExtFromI1(EVT::i8, ResultReg);
if (ResultReg == 0) return false;
UpdateValueMap(I, ResultReg);
return true;
@@ -798,7 +798,7 @@
// Fold the common case of a conditional branch with a comparison.
if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
if (CI->hasOneUse()) {
- MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
+ EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
// Try to take advantage of fallthrough opportunities.
CmpInst::Predicate Predicate = CI->getPredicate();
@@ -975,8 +975,8 @@
return false;
}
- MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
+ EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
+ if (VT == EVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0));
@@ -1009,19 +1009,19 @@
}
bool X86FastISel::X86SelectSelect(Instruction *I) {
- MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
+ EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
+ if (VT == EVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- if (VT.getSimpleVT() == MVT::i16) {
+ if (VT.getSimpleVT() == EVT::i16) {
Opc = X86::CMOVE16rr;
RC = &X86::GR16RegClass;
- } else if (VT.getSimpleVT() == MVT::i32) {
+ } else if (VT.getSimpleVT() == EVT::i32) {
Opc = X86::CMOVE32rr;
RC = &X86::GR32RegClass;
- } else if (VT.getSimpleVT() == MVT::i64) {
+ } else if (VT.getSimpleVT() == EVT::i64) {
Opc = X86::CMOVE64rr;
RC = &X86::GR64RegClass;
} else {
@@ -1081,14 +1081,14 @@
if (Subtarget->is64Bit())
// All other cases should be handled by the tblgen generated code.
return false;
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
// This code only handles truncation to byte right now.
- if (DstVT != MVT::i8 && DstVT != MVT::i1)
+ if (DstVT != EVT::i8 && DstVT != EVT::i1)
// All other cases should be handled by the tblgen generated code.
return false;
- if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
+ if (SrcVT != EVT::i16 && SrcVT != EVT::i32)
// All other cases should be handled by the tblgen generated code.
return false;
@@ -1098,14 +1098,14 @@
return false;
// First issue a copy to GR16_ABCD or GR32_ABCD.
- unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
- const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
+ unsigned CopyOpc = (SrcVT == EVT::i16) ? X86::MOV16rr : X86::MOV32rr;
+ const TargetRegisterClass *CopyRC = (SrcVT == EVT::i16)
? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
unsigned CopyReg = createResultReg(CopyRC);
BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
// Then issue an extract_subreg.
- unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
+ unsigned ResultReg = FastEmitInst_extractsubreg(EVT::i8,
CopyReg, X86::SUBREG_8BIT);
if (!ResultReg)
return false;
@@ -1150,7 +1150,7 @@
const Type *RetTy =
cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
- MVT VT;
+ EVT VT;
if (!isTypeLegal(RetTy, VT))
return false;
@@ -1164,9 +1164,9 @@
return false;
unsigned OpC = 0;
- if (VT == MVT::i32)
+ if (VT == EVT::i32)
OpC = X86::ADD32rr;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
OpC = X86::ADD64rr;
else
return false;
@@ -1185,7 +1185,7 @@
if (DestReg1 != ResultReg)
ResultReg = DestReg1+1;
else
- ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
+ ResultReg = createResultReg(TLI.getRegClassFor(EVT::i8));
unsigned Opc = X86::SETBr;
if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
@@ -1229,9 +1229,9 @@
// Handle *simple* calls for now.
const Type *RetTy = CS.getType();
- MVT RetVT;
+ EVT RetVT;
if (RetTy == Type::VoidTy)
- RetVT = MVT::isVoid;
+ RetVT = EVT::isVoid;
else if (!isTypeLegal(RetTy, RetVT, true))
return false;
@@ -1251,15 +1251,15 @@
// Allow calls which produce i1 results.
bool AndToI1 = false;
- if (RetVT == MVT::i1) {
- RetVT = MVT::i8;
+ if (RetVT == EVT::i1) {
+ RetVT = EVT::i8;
AndToI1 = true;
}
// Deal with call operands first.
SmallVector<Value*, 8> ArgVals;
SmallVector<unsigned, 8> Args;
- SmallVector<MVT, 8> ArgVTs;
+ SmallVector<EVT, 8> ArgVTs;
SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
Args.reserve(CS.arg_size());
ArgVals.reserve(CS.arg_size());
@@ -1285,7 +1285,7 @@
return false;
const Type *ArgTy = (*i)->getType();
- MVT ArgVT;
+ EVT ArgVT;
if (!isTypeLegal(ArgTy, ArgVT))
return false;
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
@@ -1315,7 +1315,7 @@
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
unsigned Arg = Args[VA.getValNo()];
- MVT ArgVT = ArgVTs[VA.getValNo()];
+ EVT ArgVT = ArgVTs[VA.getValNo()];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -1445,14 +1445,14 @@
BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
// Now handle call return value (if any).
- if (RetVT.getSimpleVT() != MVT::isVoid) {
+ if (RetVT.getSimpleVT() != EVT::isVoid) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
// Copy all of the result registers out of their specified physreg.
assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
- MVT CopyVT = RVLocs[0].getValVT();
+ EVT CopyVT = RVLocs[0].getValVT();
TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
TargetRegisterClass *SrcRC = DstRC;
@@ -1462,7 +1462,7 @@
if ((RVLocs[0].getLocReg() == X86::ST0 ||
RVLocs[0].getLocReg() == X86::ST1) &&
isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
- CopyVT = MVT::f80;
+ CopyVT = EVT::f80;
SrcRC = X86::RSTRegisterClass;
DstRC = X86::RFP80RegisterClass;
}
@@ -1476,14 +1476,14 @@
// Round the F80 the right size, which also moves to the appropriate xmm
// register. This is accomplished by storing the F80 value in memory and
// then loading it back. Ewww...
- MVT ResVT = RVLocs[0].getValVT();
- unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
+ EVT ResVT = RVLocs[0].getValVT();
+ unsigned Opc = ResVT == EVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
unsigned MemSize = ResVT.getSizeInBits()/8;
int FI = MFI.CreateStackObject(MemSize, MemSize);
addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
- DstRC = ResVT == MVT::f32
+ DstRC = ResVT == EVT::f32
? X86::FR32RegisterClass : X86::FR64RegisterClass;
- Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
+ Opc = ResVT == EVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
ResultReg = createResultReg(DstRC);
addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
}
@@ -1536,8 +1536,8 @@
return X86SelectExtractValue(I);
case Instruction::IntToPtr: // Deliberate fall-through.
case Instruction::PtrToInt: {
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
if (DstVT.bitsGT(SrcVT))
return X86SelectZExt(I);
if (DstVT.bitsLT(SrcVT))
@@ -1553,7 +1553,7 @@
}
unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
- MVT VT;
+ EVT VT;
if (!isTypeLegal(C->getType(), VT))
return false;
@@ -1562,24 +1562,24 @@
const TargetRegisterClass *RC = NULL;
switch (VT.getSimpleVT()) {
default: return false;
- case MVT::i8:
+ case EVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
break;
- case MVT::i16:
+ case EVT::i16:
Opc = X86::MOV16rm;
RC = X86::GR16RegisterClass;
break;
- case MVT::i32:
+ case EVT::i32:
Opc = X86::MOV32rm;
RC = X86::GR32RegisterClass;
break;
- case MVT::i64:
+ case EVT::i64:
// Must be in x86-64 mode.
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
break;
- case MVT::f32:
+ case EVT::f32:
if (Subtarget->hasSSE1()) {
Opc = X86::MOVSSrm;
RC = X86::FR32RegisterClass;
@@ -1588,7 +1588,7 @@
RC = X86::RFP32RegisterClass;
}
break;
- case MVT::f64:
+ case EVT::f64:
if (Subtarget->hasSSE2()) {
Opc = X86::MOVSDrm;
RC = X86::FR64RegisterClass;
@@ -1597,7 +1597,7 @@
RC = X86::RFP64RegisterClass;
}
break;
- case MVT::f80:
+ case EVT::f80:
// No f80 support yet.
return false;
}
@@ -1606,7 +1606,7 @@
if (isa<GlobalValue>(C)) {
X86AddressMode AM;
if (X86SelectAddress(C, AM)) {
- if (TLI.getPointerTy() == MVT::i32)
+ if (TLI.getPointerTy() == EVT::i32)
Opc = X86::LEA32r;
else
Opc = X86::LEA64r;
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 1a99b08..4aee493 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -186,7 +186,7 @@
private:
SDNode *Select(SDValue N);
SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
- SDNode *SelectAtomicLoadAdd(SDNode *Node, MVT NVT);
+ SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
@@ -233,40 +233,40 @@
// These are 32-bit even in 64-bit mode since RIP relative offset
// is 32-bit.
if (AM.GV)
- Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
+ Disp = CurDAG->getTargetGlobalAddress(AM.GV, EVT::i32, AM.Disp,
AM.SymbolFlags);
else if (AM.CP)
- Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
+ Disp = CurDAG->getTargetConstantPool(AM.CP, EVT::i32,
AM.Align, AM.Disp, AM.SymbolFlags);
else if (AM.ES)
- Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
+ Disp = CurDAG->getTargetExternalSymbol(AM.ES, EVT::i32, AM.SymbolFlags);
else if (AM.JT != -1)
- Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
+ Disp = CurDAG->getTargetJumpTable(AM.JT, EVT::i32, AM.SymbolFlags);
else
- Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
+ Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i32);
if (AM.Segment.getNode())
Segment = AM.Segment;
else
- Segment = CurDAG->getRegister(0, MVT::i32);
+ Segment = CurDAG->getRegister(0, EVT::i32);
}
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDValue getI8Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i8);
+ return CurDAG->getTargetConstant(Imm, EVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i16);
+ return CurDAG->getTargetConstant(Imm, EVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i32);
+ return CurDAG->getTargetConstant(Imm, EVT::i32);
}
/// getGlobalBaseReg - Return an SDNode that returns the value of
@@ -408,7 +408,7 @@
Ops.push_back(Chain.getOperand(i));
SDValue NewChain =
CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
- MVT::Other, &Ops[0], Ops.size());
+ EVT::Other, &Ops[0], Ops.size());
Ops.clear();
Ops.push_back(NewChain);
}
@@ -599,8 +599,8 @@
// If the source and destination are SSE registers, then this is a legal
// conversion that should not be lowered.
- MVT SrcVT = N->getOperand(0).getValueType();
- MVT DstVT = N->getValueType(0);
+ EVT SrcVT = N->getOperand(0).getValueType();
+ EVT DstVT = N->getValueType(0);
bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
if (SrcIsSSE && DstIsSSE)
@@ -618,7 +618,7 @@
// Here we could have an FP stack truncation or an FPStack <-> SSE convert.
// FPStack has extload and truncstore. SSE can fold direct loads into other
// operations. Based on this, decide what we want to do.
- MVT MemVT;
+ EVT MemVT;
if (N->getOpcode() == ISD::FP_ROUND)
MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
else
@@ -764,7 +764,7 @@
}
if (N.getOpcode() == X86ISD::WrapperRIP)
- AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
+ AM.setBaseReg(CurDAG->getRegister(X86::RIP, EVT::i64));
return false;
}
@@ -1001,7 +1001,7 @@
RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
(RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
- RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
+ RHS.getNode()->getOperand(0).getValueType() == EVT::i32))
++Cost;
// If the base is a register with multiple uses, this
// transformation may save a mov.
@@ -1111,13 +1111,13 @@
unsigned ScaleLog = 8 - C1->getZExtValue();
if (ScaleLog > 0 && ScaleLog < 4 &&
C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
- SDValue Eight = CurDAG->getConstant(8, MVT::i8);
+ SDValue Eight = CurDAG->getConstant(8, EVT::i8);
SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
X, Eight);
SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
Srl, Mask);
- SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
+ SDValue ShlCount = CurDAG->getConstant(ScaleLog, EVT::i8);
SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
And, ShlCount);
@@ -1267,7 +1267,7 @@
if (!Done && MatchAddress(N, AM))
return false;
- MVT VT = N.getValueType();
+ EVT VT = N.getValueType();
if (AM.BaseType == X86ISelAddressMode::RegBase) {
if (!AM.Base.Reg.getNode())
AM.Base.Reg = CurDAG->getRegister(0, VT);
@@ -1333,14 +1333,14 @@
// Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
// segments.
SDValue Copy = AM.Segment;
- SDValue T = CurDAG->getRegister(0, MVT::i32);
+ SDValue T = CurDAG->getRegister(0, EVT::i32);
AM.Segment = T;
if (MatchAddress(N, AM))
return false;
assert (T == AM.Segment);
AM.Segment = Copy;
- MVT VT = N.getValueType();
+ EVT VT = N.getValueType();
unsigned Complexity = 0;
if (AM.BaseType == X86ISelAddressMode::RegBase)
if (AM.Base.Reg.getNode())
@@ -1400,11 +1400,11 @@
AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
AM.SymbolFlags = GA->getTargetFlags();
- if (N.getValueType() == MVT::i32) {
+ if (N.getValueType() == EVT::i32) {
AM.Scale = 1;
- AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
+ AM.IndexReg = CurDAG->getRegister(X86::EBX, EVT::i32);
} else {
- AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
+ AM.IndexReg = CurDAG->getRegister(0, EVT::i64);
}
SDValue Segment;
@@ -1435,7 +1435,7 @@
static SDNode *FindCallStartFromCall(SDNode *Node) {
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
- assert(Node->getOperand(0).getValueType() == MVT::Other &&
+ assert(Node->getOperand(0).getValueType() == EVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCall(Node->getOperand(0).getNode());
}
@@ -1451,11 +1451,11 @@
SDValue LSI = Node->getOperand(4); // MemOperand
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
- MVT::i32, MVT::i32, MVT::Other, Ops,
+ EVT::i32, EVT::i32, EVT::Other, Ops,
array_lengthof(Ops));
}
-SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) {
+SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
if (Node->hasAnyUseOfValue(0))
return 0;
@@ -1497,7 +1497,7 @@
unsigned Opc = 0;
switch (NVT.getSimpleVT()) {
default: return 0;
- case MVT::i8:
+ case EVT::i8:
if (isInc)
Opc = X86::LOCK_INC8m;
else if (isDec)
@@ -1514,7 +1514,7 @@
Opc = X86::LOCK_ADD8mr;
}
break;
- case MVT::i16:
+ case EVT::i16:
if (isInc)
Opc = X86::LOCK_INC16m;
else if (isDec)
@@ -1537,7 +1537,7 @@
Opc = X86::LOCK_ADD16mr;
}
break;
- case MVT::i32:
+ case EVT::i32:
if (isInc)
Opc = X86::LOCK_INC32m;
else if (isDec)
@@ -1560,7 +1560,7 @@
Opc = X86::LOCK_ADD32mr;
}
break;
- case MVT::i64:
+ case EVT::i64:
if (isInc)
Opc = X86::LOCK_INC64m;
else if (isDec)
@@ -1591,12 +1591,12 @@
SDValue MemOp = CurDAG->getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
if (isInc || isDec) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0);
+ SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7), 0);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
} else {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0);
+ SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 8), 0);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
}
@@ -1604,7 +1604,7 @@
SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDNode *Node = N.getNode();
- MVT NVT = Node->getValueType(0);
+ EVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
unsigned Opcode = Node->getOpcode();
DebugLoc dl = Node->getDebugLoc();
@@ -1666,28 +1666,28 @@
if (!isSigned) {
switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!");
- case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
- case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
- case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
- case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
+ case EVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
+ case EVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
+ case EVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
+ case EVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
}
} else {
switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!");
- case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
- case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
- case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
- case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
+ case EVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
+ case EVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
+ case EVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
+ case EVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
}
}
unsigned LoReg, HiReg;
switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!");
- case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
- case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
- case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
- case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
+ case EVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
+ case EVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
+ case EVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
+ case EVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
}
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
@@ -1706,14 +1706,14 @@
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
+ CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops,
array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
@@ -1737,15 +1737,15 @@
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- X86::AX, MVT::i16, InFlag);
+ X86::AX, EVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16,
Result,
- CurDAG->getTargetConstant(8, MVT::i8)), 0);
+ CurDAG->getTargetConstant(8, EVT::i8)), 0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
+ SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32);
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- MVT::i8, Result, SRIdx), 0);
+ EVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
@@ -1777,18 +1777,18 @@
if (!isSigned) {
switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!");
- case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
- case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
- case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
- case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
+ case EVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
+ case EVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
+ case EVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
+ case EVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
}
} else {
switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!");
- case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
- case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
- case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
- case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
+ case EVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
+ case EVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
+ case EVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
+ case EVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
}
}
@@ -1796,22 +1796,22 @@
unsigned ClrOpcode, SExtOpcode;
switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!");
- case MVT::i8:
+ case EVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
ClrOpcode = 0;
SExtOpcode = X86::CBW;
break;
- case MVT::i16:
+ case EVT::i16:
LoReg = X86::AX; HiReg = X86::DX;
ClrOpcode = X86::MOV16r0;
SExtOpcode = X86::CWD;
break;
- case MVT::i32:
+ case EVT::i32:
LoReg = X86::EAX; HiReg = X86::EDX;
ClrOpcode = X86::MOV32r0;
SExtOpcode = X86::CDQ;
break;
- case MVT::i64:
+ case EVT::i64:
LoReg = X86::RAX; HiReg = X86::RDX;
ClrOpcode = ~0U; // NOT USED.
SExtOpcode = X86::CQO;
@@ -1823,21 +1823,21 @@
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
SDValue InFlag;
- if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
+ if (NVT == EVT::i8 && (!isSigned || signBitIsZero)) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
- MVT::Other, Ops,
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, EVT::i16,
+ EVT::Other, Ops,
array_lengthof(Ops)), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, EVT::i16, N0),0);
Chain = CurDAG->getEntryNode();
}
Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
@@ -1849,24 +1849,24 @@
if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
- SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
+ SDValue(CurDAG->getTargetNode(SExtOpcode, dl, EVT::Flag, InFlag),0);
} else {
// Zero out the high part, effectively zero extending the input.
SDValue ClrNode;
- if (NVT.getSimpleVT() == MVT::i64) {
- ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32),
+ if (NVT.getSimpleVT() == EVT::i64) {
+ ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, EVT::i32),
0);
// We just did a 32-bit clear, insert it into a 64-bit register to
// clear the whole 64-bit reg.
SDValue Undef =
SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
- dl, MVT::i64), 0);
+ dl, EVT::i64), 0);
SDValue SubRegNo =
- CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
+ CurDAG->getTargetConstant(X86::SUBREG_32BIT, EVT::i32);
ClrNode =
SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl,
- MVT::i64, Undef, ClrNode, SubRegNo),
+ EVT::i64, Undef, ClrNode, SubRegNo),
0);
} else {
ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0);
@@ -1881,14 +1881,14 @@
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
+ CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops,
array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
@@ -1912,16 +1912,16 @@
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- X86::AX, MVT::i16, InFlag);
+ X86::AX, EVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16,
Result,
- CurDAG->getTargetConstant(8, MVT::i8)),
+ CurDAG->getTargetConstant(8, EVT::i8)),
0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
+ SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32);
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- MVT::i8, Result, SRIdx), 0);
+ EVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
@@ -1981,7 +1981,7 @@
TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
- MVT::Other, Ops,
+ EVT::Other, Ops,
array_lengthof(Ops));
}
}
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 3fbb846..8551673 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -48,7 +48,7 @@
DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
// Forward declarations.
-static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2);
static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
@@ -79,7 +79,7 @@
// Set up the TargetLowering object.
// X86 is weird, it always uses i8 for shift amounts and setcc results.
- setShiftAmountType(MVT::i8);
+ setShiftAmountType(EVT::i8);
setBooleanContents(ZeroOrOneBooleanContent);
setSchedulingPreference(SchedulingForRegPressure);
setStackPointerRegisterToSaveRestore(X86StackPtr);
@@ -98,113 +98,113 @@
}
// Set up the register classes.
- addRegisterClass(MVT::i8, X86::GR8RegisterClass);
- addRegisterClass(MVT::i16, X86::GR16RegisterClass);
- addRegisterClass(MVT::i32, X86::GR32RegisterClass);
+ addRegisterClass(EVT::i8, X86::GR8RegisterClass);
+ addRegisterClass(EVT::i16, X86::GR16RegisterClass);
+ addRegisterClass(EVT::i32, X86::GR32RegisterClass);
if (Subtarget->is64Bit())
- addRegisterClass(MVT::i64, X86::GR64RegisterClass);
+ addRegisterClass(EVT::i64, X86::GR64RegisterClass);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
// We don't accept any truncstore of integer registers.
- setTruncStoreAction(MVT::i64, MVT::i32, Expand);
- setTruncStoreAction(MVT::i64, MVT::i16, Expand);
- setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
- setTruncStoreAction(MVT::i32, MVT::i16, Expand);
- setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
- setTruncStoreAction(MVT::i16, MVT::i8, Expand);
+ setTruncStoreAction(EVT::i64, EVT::i32, Expand);
+ setTruncStoreAction(EVT::i64, EVT::i16, Expand);
+ setTruncStoreAction(EVT::i64, EVT::i8 , Expand);
+ setTruncStoreAction(EVT::i32, EVT::i16, Expand);
+ setTruncStoreAction(EVT::i32, EVT::i8 , Expand);
+ setTruncStoreAction(EVT::i16, EVT::i8, Expand);
// SETOEQ and SETUNE require checking two conditions.
- setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
- setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
- setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
- setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
- setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
- setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
+ setCondCodeAction(ISD::SETOEQ, EVT::f32, Expand);
+ setCondCodeAction(ISD::SETOEQ, EVT::f64, Expand);
+ setCondCodeAction(ISD::SETOEQ, EVT::f80, Expand);
+ setCondCodeAction(ISD::SETUNE, EVT::f32, Expand);
+ setCondCodeAction(ISD::SETUNE, EVT::f64, Expand);
+ setCondCodeAction(ISD::SETUNE, EVT::f80, Expand);
// Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
// operation.
- setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
- setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
- setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , EVT::i1 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , EVT::i8 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , EVT::i16 , Promote);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
- setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
+ setOperationAction(ISD::UINT_TO_FP , EVT::i32 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , EVT::i64 , Expand);
} else if (!UseSoftFloat) {
if (X86ScalarSSEf64) {
// We have an impenetrably clever algorithm for ui64->double only.
- setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
+ setOperationAction(ISD::UINT_TO_FP , EVT::i64 , Custom);
}
// We have an algorithm for SSE2, and we turn this into a 64-bit
// FILD for other targets.
- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
+ setOperationAction(ISD::UINT_TO_FP , EVT::i32 , Custom);
}
// Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
// this operation.
- setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
- setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i1 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i8 , Promote);
if (!UseSoftFloat) {
// SSE has no i16 to fp conversion, only i32
if (X86ScalarSSEf32) {
- setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Promote);
// f32 and f64 cases are Legal, f80 case is not
- setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Custom);
} else {
- setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
- setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Custom);
}
} else {
- setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
- setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Promote);
}
// In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
// are Legal, f80 is custom lowered.
- setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
- setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , EVT::i64 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , EVT::i64 , Custom);
// Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
// this operation.
- setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
- setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , EVT::i1 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , EVT::i8 , Promote);
if (X86ScalarSSEf32) {
- setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , EVT::i16 , Promote);
// f32 and f64 cases are Legal, f80 case is not
- setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , EVT::i32 , Custom);
} else {
- setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
- setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , EVT::i16 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , EVT::i32 , Custom);
}
// Handle FP_TO_UINT by promoting the destination to a larger signed
// conversion.
- setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
- setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
- setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , EVT::i1 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , EVT::i8 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , EVT::i16 , Promote);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
- setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , EVT::i64 , Expand);
+ setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Promote);
} else if (!UseSoftFloat) {
if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
// Expand FP_TO_UINT into a select.
// FIXME: We would like to use a Custom expander here eventually to do
// the optimal thing for SSE vs. the default expansion in the legalizer.
- setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
+ setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Expand);
else
// With SSE3 we can use fisttpll to convert to a signed i64; without
// SSE, we're stuck with a fistpll.
- setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
+ setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Custom);
}
// TODO: when we have SSE, these could be more efficient, by using movd/movq.
if (!X86ScalarSSEf64) {
- setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
- setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
+ setOperationAction(ISD::BIT_CONVERT , EVT::f32 , Expand);
+ setOperationAction(ISD::BIT_CONVERT , EVT::i32 , Expand);
}
// Scalar integer divide and remainder are lowered to use operations that
@@ -217,150 +217,150 @@
// (low) operations are left as Legal, as there are single-result
// instructions for this in x86. Using the two-result multiply instructions
// when both high and low results are needed must be arranged by dagcombine.
- setOperationAction(ISD::MULHS , MVT::i8 , Expand);
- setOperationAction(ISD::MULHU , MVT::i8 , Expand);
- setOperationAction(ISD::SDIV , MVT::i8 , Expand);
- setOperationAction(ISD::UDIV , MVT::i8 , Expand);
- setOperationAction(ISD::SREM , MVT::i8 , Expand);
- setOperationAction(ISD::UREM , MVT::i8 , Expand);
- setOperationAction(ISD::MULHS , MVT::i16 , Expand);
- setOperationAction(ISD::MULHU , MVT::i16 , Expand);
- setOperationAction(ISD::SDIV , MVT::i16 , Expand);
- setOperationAction(ISD::UDIV , MVT::i16 , Expand);
- setOperationAction(ISD::SREM , MVT::i16 , Expand);
- setOperationAction(ISD::UREM , MVT::i16 , Expand);
- setOperationAction(ISD::MULHS , MVT::i32 , Expand);
- setOperationAction(ISD::MULHU , MVT::i32 , Expand);
- setOperationAction(ISD::SDIV , MVT::i32 , Expand);
- setOperationAction(ISD::UDIV , MVT::i32 , Expand);
- setOperationAction(ISD::SREM , MVT::i32 , Expand);
- setOperationAction(ISD::UREM , MVT::i32 , Expand);
- setOperationAction(ISD::MULHS , MVT::i64 , Expand);
- setOperationAction(ISD::MULHU , MVT::i64 , Expand);
- setOperationAction(ISD::SDIV , MVT::i64 , Expand);
- setOperationAction(ISD::UDIV , MVT::i64 , Expand);
- setOperationAction(ISD::SREM , MVT::i64 , Expand);
- setOperationAction(ISD::UREM , MVT::i64 , Expand);
+ setOperationAction(ISD::MULHS , EVT::i8 , Expand);
+ setOperationAction(ISD::MULHU , EVT::i8 , Expand);
+ setOperationAction(ISD::SDIV , EVT::i8 , Expand);
+ setOperationAction(ISD::UDIV , EVT::i8 , Expand);
+ setOperationAction(ISD::SREM , EVT::i8 , Expand);
+ setOperationAction(ISD::UREM , EVT::i8 , Expand);
+ setOperationAction(ISD::MULHS , EVT::i16 , Expand);
+ setOperationAction(ISD::MULHU , EVT::i16 , Expand);
+ setOperationAction(ISD::SDIV , EVT::i16 , Expand);
+ setOperationAction(ISD::UDIV , EVT::i16 , Expand);
+ setOperationAction(ISD::SREM , EVT::i16 , Expand);
+ setOperationAction(ISD::UREM , EVT::i16 , Expand);
+ setOperationAction(ISD::MULHS , EVT::i32 , Expand);
+ setOperationAction(ISD::MULHU , EVT::i32 , Expand);
+ setOperationAction(ISD::SDIV , EVT::i32 , Expand);
+ setOperationAction(ISD::UDIV , EVT::i32 , Expand);
+ setOperationAction(ISD::SREM , EVT::i32 , Expand);
+ setOperationAction(ISD::UREM , EVT::i32 , Expand);
+ setOperationAction(ISD::MULHS , EVT::i64 , Expand);
+ setOperationAction(ISD::MULHU , EVT::i64 , Expand);
+ setOperationAction(ISD::SDIV , EVT::i64 , Expand);
+ setOperationAction(ISD::UDIV , EVT::i64 , Expand);
+ setOperationAction(ISD::SREM , EVT::i64 , Expand);
+ setOperationAction(ISD::UREM , EVT::i64 , Expand);
- setOperationAction(ISD::BR_JT , MVT::Other, Expand);
- setOperationAction(ISD::BRCOND , MVT::Other, Custom);
- setOperationAction(ISD::BR_CC , MVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT , EVT::Other, Expand);
+ setOperationAction(ISD::BRCOND , EVT::Other, Custom);
+ setOperationAction(ISD::BR_CC , EVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC , EVT::Other, Expand);
if (Subtarget->is64Bit())
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
- setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
- setOperationAction(ISD::FREM , MVT::f32 , Expand);
- setOperationAction(ISD::FREM , MVT::f64 , Expand);
- setOperationAction(ISD::FREM , MVT::f80 , Expand);
- setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i32, Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16 , Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8 , Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1 , Expand);
+ setOperationAction(ISD::FP_ROUND_INREG , EVT::f32 , Expand);
+ setOperationAction(ISD::FREM , EVT::f32 , Expand);
+ setOperationAction(ISD::FREM , EVT::f64 , Expand);
+ setOperationAction(ISD::FREM , EVT::f80 , Expand);
+ setOperationAction(ISD::FLT_ROUNDS_ , EVT::i32 , Custom);
- setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
- setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
- setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
- setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
- setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
- setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
- setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
- setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
- setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
+ setOperationAction(ISD::CTPOP , EVT::i8 , Expand);
+ setOperationAction(ISD::CTTZ , EVT::i8 , Custom);
+ setOperationAction(ISD::CTLZ , EVT::i8 , Custom);
+ setOperationAction(ISD::CTPOP , EVT::i16 , Expand);
+ setOperationAction(ISD::CTTZ , EVT::i16 , Custom);
+ setOperationAction(ISD::CTLZ , EVT::i16 , Custom);
+ setOperationAction(ISD::CTPOP , EVT::i32 , Expand);
+ setOperationAction(ISD::CTTZ , EVT::i32 , Custom);
+ setOperationAction(ISD::CTLZ , EVT::i32 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
- setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
- setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
+ setOperationAction(ISD::CTPOP , EVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , EVT::i64 , Custom);
+ setOperationAction(ISD::CTLZ , EVT::i64 , Custom);
}
- setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
- setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
+ setOperationAction(ISD::READCYCLECOUNTER , EVT::i64 , Custom);
+ setOperationAction(ISD::BSWAP , EVT::i16 , Expand);
// These should be promoted to a larger select which is supported.
- setOperationAction(ISD::SELECT , MVT::i1 , Promote);
- setOperationAction(ISD::SELECT , MVT::i8 , Promote);
+ setOperationAction(ISD::SELECT , EVT::i1 , Promote);
+ setOperationAction(ISD::SELECT , EVT::i8 , Promote);
// X86 wants to expand cmov itself.
- setOperationAction(ISD::SELECT , MVT::i16 , Custom);
- setOperationAction(ISD::SELECT , MVT::i32 , Custom);
- setOperationAction(ISD::SELECT , MVT::f32 , Custom);
- setOperationAction(ISD::SELECT , MVT::f64 , Custom);
- setOperationAction(ISD::SELECT , MVT::f80 , Custom);
- setOperationAction(ISD::SETCC , MVT::i8 , Custom);
- setOperationAction(ISD::SETCC , MVT::i16 , Custom);
- setOperationAction(ISD::SETCC , MVT::i32 , Custom);
- setOperationAction(ISD::SETCC , MVT::f32 , Custom);
- setOperationAction(ISD::SETCC , MVT::f64 , Custom);
- setOperationAction(ISD::SETCC , MVT::f80 , Custom);
+ setOperationAction(ISD::SELECT , EVT::i16 , Custom);
+ setOperationAction(ISD::SELECT , EVT::i32 , Custom);
+ setOperationAction(ISD::SELECT , EVT::f32 , Custom);
+ setOperationAction(ISD::SELECT , EVT::f64 , Custom);
+ setOperationAction(ISD::SELECT , EVT::f80 , Custom);
+ setOperationAction(ISD::SETCC , EVT::i8 , Custom);
+ setOperationAction(ISD::SETCC , EVT::i16 , Custom);
+ setOperationAction(ISD::SETCC , EVT::i32 , Custom);
+ setOperationAction(ISD::SETCC , EVT::f32 , Custom);
+ setOperationAction(ISD::SETCC , EVT::f64 , Custom);
+ setOperationAction(ISD::SETCC , EVT::f80 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::SELECT , MVT::i64 , Custom);
- setOperationAction(ISD::SETCC , MVT::i64 , Custom);
+ setOperationAction(ISD::SELECT , EVT::i64 , Custom);
+ setOperationAction(ISD::SETCC , EVT::i64 , Custom);
}
- setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
+ setOperationAction(ISD::EH_RETURN , EVT::Other, Custom);
// Darwin ABI issue.
- setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
- setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
- setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
- setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
+ setOperationAction(ISD::ConstantPool , EVT::i32 , Custom);
+ setOperationAction(ISD::JumpTable , EVT::i32 , Custom);
+ setOperationAction(ISD::GlobalAddress , EVT::i32 , Custom);
+ setOperationAction(ISD::GlobalTLSAddress, EVT::i32 , Custom);
if (Subtarget->is64Bit())
- setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
- setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
+ setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom);
+ setOperationAction(ISD::ExternalSymbol , EVT::i32 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
- setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
- setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
- setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
+ setOperationAction(ISD::ConstantPool , EVT::i64 , Custom);
+ setOperationAction(ISD::JumpTable , EVT::i64 , Custom);
+ setOperationAction(ISD::GlobalAddress , EVT::i64 , Custom);
+ setOperationAction(ISD::ExternalSymbol, EVT::i64 , Custom);
}
// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
- setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
- setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
- setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
+ setOperationAction(ISD::SHL_PARTS , EVT::i32 , Custom);
+ setOperationAction(ISD::SRA_PARTS , EVT::i32 , Custom);
+ setOperationAction(ISD::SRL_PARTS , EVT::i32 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
- setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
- setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
+ setOperationAction(ISD::SHL_PARTS , EVT::i64 , Custom);
+ setOperationAction(ISD::SRA_PARTS , EVT::i64 , Custom);
+ setOperationAction(ISD::SRL_PARTS , EVT::i64 , Custom);
}
if (Subtarget->hasSSE1())
- setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
+ setOperationAction(ISD::PREFETCH , EVT::Other, Legal);
if (!Subtarget->hasSSE2())
- setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER , EVT::Other, Expand);
// Expand certain atomics
- setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
- setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
- setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
- setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i8, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i16, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i32, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i8, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i16, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i32, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i64, Custom);
if (!Subtarget->is64Bit()) {
- setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_ADD, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_AND, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_OR, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_XOR, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_NAND, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_SWAP, EVT::i64, Custom);
}
// Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
- setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
// FIXME - use subtarget debug flags
if (!Subtarget->isTargetDarwin() &&
!Subtarget->isTargetELF() &&
!Subtarget->isTargetCygMing()) {
- setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
}
- setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
- setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
- setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
- setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, EVT::i64, Expand);
+ setOperationAction(ISD::EHSELECTION, EVT::i64, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, EVT::i32, Expand);
+ setOperationAction(ISD::EHSELECTION, EVT::i32, Expand);
if (Subtarget->is64Bit()) {
setExceptionPointerRegister(X86::RAX);
setExceptionSelectorRegister(X86::RDX);
@@ -368,56 +368,56 @@
setExceptionPointerRegister(X86::EAX);
setExceptionSelectorRegister(X86::EDX);
}
- setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
- setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
+ setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, EVT::i32, Custom);
+ setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, EVT::i64, Custom);
- setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
+ setOperationAction(ISD::TRAMPOLINE, EVT::Other, Custom);
- setOperationAction(ISD::TRAP, MVT::Other, Legal);
+ setOperationAction(ISD::TRAP, EVT::Other, Legal);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VASTART , MVT::Other, Custom);
- setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::VASTART , EVT::Other, Custom);
+ setOperationAction(ISD::VAEND , EVT::Other, Expand);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::VAARG , MVT::Other, Custom);
- setOperationAction(ISD::VACOPY , MVT::Other, Custom);
+ setOperationAction(ISD::VAARG , EVT::Other, Custom);
+ setOperationAction(ISD::VACOPY , EVT::Other, Custom);
} else {
- setOperationAction(ISD::VAARG , MVT::Other, Expand);
- setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAARG , EVT::Other, Expand);
+ setOperationAction(ISD::VACOPY , EVT::Other, Expand);
}
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
if (Subtarget->is64Bit())
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
if (Subtarget->isTargetCygMing())
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
else
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand);
if (!UseSoftFloat && X86ScalarSSEf64) {
// f32 and f64 use SSE.
// Set up the FP register classes.
- addRegisterClass(MVT::f32, X86::FR32RegisterClass);
- addRegisterClass(MVT::f64, X86::FR64RegisterClass);
+ addRegisterClass(EVT::f32, X86::FR32RegisterClass);
+ addRegisterClass(EVT::f64, X86::FR64RegisterClass);
// Use ANDPD to simulate FABS.
- setOperationAction(ISD::FABS , MVT::f64, Custom);
- setOperationAction(ISD::FABS , MVT::f32, Custom);
+ setOperationAction(ISD::FABS , EVT::f64, Custom);
+ setOperationAction(ISD::FABS , EVT::f32, Custom);
// Use XORP to simulate FNEG.
- setOperationAction(ISD::FNEG , MVT::f64, Custom);
- setOperationAction(ISD::FNEG , MVT::f32, Custom);
+ setOperationAction(ISD::FNEG , EVT::f64, Custom);
+ setOperationAction(ISD::FNEG , EVT::f32, Custom);
// Use ANDPD and ORPD to simulate FCOPYSIGN.
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f64, Custom);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom);
// We don't support sin/cos/fmod
- setOperationAction(ISD::FSIN , MVT::f64, Expand);
- setOperationAction(ISD::FCOS , MVT::f64, Expand);
- setOperationAction(ISD::FSIN , MVT::f32, Expand);
- setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FSIN , EVT::f64, Expand);
+ setOperationAction(ISD::FCOS , EVT::f64, Expand);
+ setOperationAction(ISD::FSIN , EVT::f32, Expand);
+ setOperationAction(ISD::FCOS , EVT::f32, Expand);
// Expand FP immediates into loads from the stack, except for the special
// cases we handle.
@@ -426,24 +426,24 @@
} else if (!UseSoftFloat && X86ScalarSSEf32) {
// Use SSE for f32, x87 for f64.
// Set up the FP register classes.
- addRegisterClass(MVT::f32, X86::FR32RegisterClass);
- addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
+ addRegisterClass(EVT::f32, X86::FR32RegisterClass);
+ addRegisterClass(EVT::f64, X86::RFP64RegisterClass);
// Use ANDPS to simulate FABS.
- setOperationAction(ISD::FABS , MVT::f32, Custom);
+ setOperationAction(ISD::FABS , EVT::f32, Custom);
// Use XORP to simulate FNEG.
- setOperationAction(ISD::FNEG , MVT::f32, Custom);
+ setOperationAction(ISD::FNEG , EVT::f32, Custom);
- setOperationAction(ISD::UNDEF, MVT::f64, Expand);
+ setOperationAction(ISD::UNDEF, EVT::f64, Expand);
// Use ANDPS and ORPS to simulate FCOPYSIGN.
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom);
// We don't support sin/cos/fmod
- setOperationAction(ISD::FSIN , MVT::f32, Expand);
- setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FSIN , EVT::f32, Expand);
+ setOperationAction(ISD::FCOS , EVT::f32, Expand);
// Special cases we handle for FP constants.
addLegalFPImmediate(APFloat(+0.0f)); // xorps
@@ -453,23 +453,23 @@
addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
if (!UnsafeFPMath) {
- setOperationAction(ISD::FSIN , MVT::f64 , Expand);
- setOperationAction(ISD::FCOS , MVT::f64 , Expand);
+ setOperationAction(ISD::FSIN , EVT::f64 , Expand);
+ setOperationAction(ISD::FCOS , EVT::f64 , Expand);
}
} else if (!UseSoftFloat) {
// f32 and f64 in x87.
// Set up the FP register classes.
- addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
- addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
+ addRegisterClass(EVT::f64, X86::RFP64RegisterClass);
+ addRegisterClass(EVT::f32, X86::RFP32RegisterClass);
- setOperationAction(ISD::UNDEF, MVT::f64, Expand);
- setOperationAction(ISD::UNDEF, MVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ setOperationAction(ISD::UNDEF, EVT::f64, Expand);
+ setOperationAction(ISD::UNDEF, EVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
if (!UnsafeFPMath) {
- setOperationAction(ISD::FSIN , MVT::f64 , Expand);
- setOperationAction(ISD::FCOS , MVT::f64 , Expand);
+ setOperationAction(ISD::FSIN , EVT::f64 , Expand);
+ setOperationAction(ISD::FCOS , EVT::f64 , Expand);
}
addLegalFPImmediate(APFloat(+0.0)); // FLD0
addLegalFPImmediate(APFloat(+1.0)); // FLD1
@@ -483,9 +483,9 @@
// Long double always uses X87.
if (!UseSoftFloat) {
- addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
- setOperationAction(ISD::UNDEF, MVT::f80, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
+ addRegisterClass(EVT::f80, X86::RFP80RegisterClass);
+ setOperationAction(ISD::UNDEF, EVT::f80, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f80, Expand);
{
bool ignored;
APFloat TmpFlt(+0.0);
@@ -503,220 +503,220 @@
}
if (!UnsafeFPMath) {
- setOperationAction(ISD::FSIN , MVT::f80 , Expand);
- setOperationAction(ISD::FCOS , MVT::f80 , Expand);
+ setOperationAction(ISD::FSIN , EVT::f80 , Expand);
+ setOperationAction(ISD::FCOS , EVT::f80 , Expand);
}
}
// Always use a library call for pow.
- setOperationAction(ISD::FPOW , MVT::f32 , Expand);
- setOperationAction(ISD::FPOW , MVT::f64 , Expand);
- setOperationAction(ISD::FPOW , MVT::f80 , Expand);
+ setOperationAction(ISD::FPOW , EVT::f32 , Expand);
+ setOperationAction(ISD::FPOW , EVT::f64 , Expand);
+ setOperationAction(ISD::FPOW , EVT::f80 , Expand);
- setOperationAction(ISD::FLOG, MVT::f80, Expand);
- setOperationAction(ISD::FLOG2, MVT::f80, Expand);
- setOperationAction(ISD::FLOG10, MVT::f80, Expand);
- setOperationAction(ISD::FEXP, MVT::f80, Expand);
- setOperationAction(ISD::FEXP2, MVT::f80, Expand);
+ setOperationAction(ISD::FLOG, EVT::f80, Expand);
+ setOperationAction(ISD::FLOG2, EVT::f80, Expand);
+ setOperationAction(ISD::FLOG10, EVT::f80, Expand);
+ setOperationAction(ISD::FEXP, EVT::f80, Expand);
+ setOperationAction(ISD::FEXP2, EVT::f80, Expand);
// First set operation action for all vector types to either promote
// (for widening) or expand (for scalarization). Then we will selectively
// turn on ones that can be effectively codegen'd.
- for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
- VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
- setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
- setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
- setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
+ for (unsigned VT = (unsigned)EVT::FIRST_VECTOR_VALUETYPE;
+ VT <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++VT) {
+ setOperationAction(ISD::ADD , (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SUB , (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FADD, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FNEG, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FSUB, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::MUL , (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FMUL, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SDIV, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UDIV, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FDIV, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SREM, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UREM, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::LOAD, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::VECTOR_SHUFFLE, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT,(EVT::SimpleValueType)VT,Expand);
+ setOperationAction(ISD::EXTRACT_SUBVECTOR,(EVT::SimpleValueType)VT,Expand);
+ setOperationAction(ISD::INSERT_VECTOR_ELT,(EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FABS, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FSIN, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FCOS, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FREM, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FPOWI, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FSQRT, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FCOPYSIGN, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SMUL_LOHI, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UMUL_LOHI, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SDIVREM, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UDIVREM, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FPOW, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CTPOP, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CTTZ, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CTLZ, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SHL, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SRA, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SRL, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::ROTL, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::ROTR, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::BSWAP, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::VSETCC, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FLOG, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FLOG2, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FLOG10, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FEXP, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FEXP2, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FP_TO_UINT, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FP_TO_SINT, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UINT_TO_FP, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SINT_TO_FP, (EVT::SimpleValueType)VT, Expand);
}
// FIXME: In order to prevent SSE instructions being expanded to MMX ones
// with -msoft-float, disable use of MMX as well.
if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
- addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
- addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
- addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
- addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
- addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
+ addRegisterClass(EVT::v8i8, X86::VR64RegisterClass);
+ addRegisterClass(EVT::v4i16, X86::VR64RegisterClass);
+ addRegisterClass(EVT::v2i32, X86::VR64RegisterClass);
+ addRegisterClass(EVT::v2f32, X86::VR64RegisterClass);
+ addRegisterClass(EVT::v1i64, X86::VR64RegisterClass);
- setOperationAction(ISD::ADD, MVT::v8i8, Legal);
- setOperationAction(ISD::ADD, MVT::v4i16, Legal);
- setOperationAction(ISD::ADD, MVT::v2i32, Legal);
- setOperationAction(ISD::ADD, MVT::v1i64, Legal);
+ setOperationAction(ISD::ADD, EVT::v8i8, Legal);
+ setOperationAction(ISD::ADD, EVT::v4i16, Legal);
+ setOperationAction(ISD::ADD, EVT::v2i32, Legal);
+ setOperationAction(ISD::ADD, EVT::v1i64, Legal);
- setOperationAction(ISD::SUB, MVT::v8i8, Legal);
- setOperationAction(ISD::SUB, MVT::v4i16, Legal);
- setOperationAction(ISD::SUB, MVT::v2i32, Legal);
- setOperationAction(ISD::SUB, MVT::v1i64, Legal);
+ setOperationAction(ISD::SUB, EVT::v8i8, Legal);
+ setOperationAction(ISD::SUB, EVT::v4i16, Legal);
+ setOperationAction(ISD::SUB, EVT::v2i32, Legal);
+ setOperationAction(ISD::SUB, EVT::v1i64, Legal);
- setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
- setOperationAction(ISD::MUL, MVT::v4i16, Legal);
+ setOperationAction(ISD::MULHS, EVT::v4i16, Legal);
+ setOperationAction(ISD::MUL, EVT::v4i16, Legal);
- setOperationAction(ISD::AND, MVT::v8i8, Promote);
- AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
- setOperationAction(ISD::AND, MVT::v4i16, Promote);
- AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
- setOperationAction(ISD::AND, MVT::v2i32, Promote);
- AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
- setOperationAction(ISD::AND, MVT::v1i64, Legal);
+ setOperationAction(ISD::AND, EVT::v8i8, Promote);
+ AddPromotedToType (ISD::AND, EVT::v8i8, EVT::v1i64);
+ setOperationAction(ISD::AND, EVT::v4i16, Promote);
+ AddPromotedToType (ISD::AND, EVT::v4i16, EVT::v1i64);
+ setOperationAction(ISD::AND, EVT::v2i32, Promote);
+ AddPromotedToType (ISD::AND, EVT::v2i32, EVT::v1i64);
+ setOperationAction(ISD::AND, EVT::v1i64, Legal);
- setOperationAction(ISD::OR, MVT::v8i8, Promote);
- AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
- setOperationAction(ISD::OR, MVT::v4i16, Promote);
- AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
- setOperationAction(ISD::OR, MVT::v2i32, Promote);
- AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
- setOperationAction(ISD::OR, MVT::v1i64, Legal);
+ setOperationAction(ISD::OR, EVT::v8i8, Promote);
+ AddPromotedToType (ISD::OR, EVT::v8i8, EVT::v1i64);
+ setOperationAction(ISD::OR, EVT::v4i16, Promote);
+ AddPromotedToType (ISD::OR, EVT::v4i16, EVT::v1i64);
+ setOperationAction(ISD::OR, EVT::v2i32, Promote);
+ AddPromotedToType (ISD::OR, EVT::v2i32, EVT::v1i64);
+ setOperationAction(ISD::OR, EVT::v1i64, Legal);
- setOperationAction(ISD::XOR, MVT::v8i8, Promote);
- AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
- setOperationAction(ISD::XOR, MVT::v4i16, Promote);
- AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
- setOperationAction(ISD::XOR, MVT::v2i32, Promote);
- AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
- setOperationAction(ISD::XOR, MVT::v1i64, Legal);
+ setOperationAction(ISD::XOR, EVT::v8i8, Promote);
+ AddPromotedToType (ISD::XOR, EVT::v8i8, EVT::v1i64);
+ setOperationAction(ISD::XOR, EVT::v4i16, Promote);
+ AddPromotedToType (ISD::XOR, EVT::v4i16, EVT::v1i64);
+ setOperationAction(ISD::XOR, EVT::v2i32, Promote);
+ AddPromotedToType (ISD::XOR, EVT::v2i32, EVT::v1i64);
+ setOperationAction(ISD::XOR, EVT::v1i64, Legal);
- setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
- AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
- setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
- AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
- setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
- AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
- setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
- AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
- setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
+ setOperationAction(ISD::LOAD, EVT::v8i8, Promote);
+ AddPromotedToType (ISD::LOAD, EVT::v8i8, EVT::v1i64);
+ setOperationAction(ISD::LOAD, EVT::v4i16, Promote);
+ AddPromotedToType (ISD::LOAD, EVT::v4i16, EVT::v1i64);
+ setOperationAction(ISD::LOAD, EVT::v2i32, Promote);
+ AddPromotedToType (ISD::LOAD, EVT::v2i32, EVT::v1i64);
+ setOperationAction(ISD::LOAD, EVT::v2f32, Promote);
+ AddPromotedToType (ISD::LOAD, EVT::v2f32, EVT::v1i64);
+ setOperationAction(ISD::LOAD, EVT::v1i64, Legal);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v8i8, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v4i16, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v2i32, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v2f32, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v1i64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v8i8, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4i16, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2i32, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v1i64, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v2f32, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v8i8, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4i16, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v1i64, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i16, Custom);
- setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
- setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
- setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
- setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
- setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
- setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
- setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
- setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
+ setTruncStoreAction(EVT::v8i16, EVT::v8i8, Expand);
+ setOperationAction(ISD::TRUNCATE, EVT::v8i8, Expand);
+ setOperationAction(ISD::SELECT, EVT::v8i8, Promote);
+ setOperationAction(ISD::SELECT, EVT::v4i16, Promote);
+ setOperationAction(ISD::SELECT, EVT::v2i32, Promote);
+ setOperationAction(ISD::SELECT, EVT::v1i64, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v8i8, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v4i16, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v2i32, Custom);
}
if (!UseSoftFloat && Subtarget->hasSSE1()) {
- addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
+ addRegisterClass(EVT::v4f32, X86::VR128RegisterClass);
- setOperationAction(ISD::FADD, MVT::v4f32, Legal);
- setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
- setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
- setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
- setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
- setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
- setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
- setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
- setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
+ setOperationAction(ISD::FADD, EVT::v4f32, Legal);
+ setOperationAction(ISD::FSUB, EVT::v4f32, Legal);
+ setOperationAction(ISD::FMUL, EVT::v4f32, Legal);
+ setOperationAction(ISD::FDIV, EVT::v4f32, Legal);
+ setOperationAction(ISD::FSQRT, EVT::v4f32, Legal);
+ setOperationAction(ISD::FNEG, EVT::v4f32, Custom);
+ setOperationAction(ISD::LOAD, EVT::v4f32, Legal);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v4f32, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4f32, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f32, Custom);
+ setOperationAction(ISD::SELECT, EVT::v4f32, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v4f32, Custom);
}
if (!UseSoftFloat && Subtarget->hasSSE2()) {
- addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
+ addRegisterClass(EVT::v2f64, X86::VR128RegisterClass);
// FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
// registers cannot be used even for integer operations.
- addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
- addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
- addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
- addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
+ addRegisterClass(EVT::v16i8, X86::VR128RegisterClass);
+ addRegisterClass(EVT::v8i16, X86::VR128RegisterClass);
+ addRegisterClass(EVT::v4i32, X86::VR128RegisterClass);
+ addRegisterClass(EVT::v2i64, X86::VR128RegisterClass);
- setOperationAction(ISD::ADD, MVT::v16i8, Legal);
- setOperationAction(ISD::ADD, MVT::v8i16, Legal);
- setOperationAction(ISD::ADD, MVT::v4i32, Legal);
- setOperationAction(ISD::ADD, MVT::v2i64, Legal);
- setOperationAction(ISD::MUL, MVT::v2i64, Custom);
- setOperationAction(ISD::SUB, MVT::v16i8, Legal);
- setOperationAction(ISD::SUB, MVT::v8i16, Legal);
- setOperationAction(ISD::SUB, MVT::v4i32, Legal);
- setOperationAction(ISD::SUB, MVT::v2i64, Legal);
- setOperationAction(ISD::MUL, MVT::v8i16, Legal);
- setOperationAction(ISD::FADD, MVT::v2f64, Legal);
- setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
- setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
- setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
- setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
- setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
+ setOperationAction(ISD::ADD, EVT::v16i8, Legal);
+ setOperationAction(ISD::ADD, EVT::v8i16, Legal);
+ setOperationAction(ISD::ADD, EVT::v4i32, Legal);
+ setOperationAction(ISD::ADD, EVT::v2i64, Legal);
+ setOperationAction(ISD::MUL, EVT::v2i64, Custom);
+ setOperationAction(ISD::SUB, EVT::v16i8, Legal);
+ setOperationAction(ISD::SUB, EVT::v8i16, Legal);
+ setOperationAction(ISD::SUB, EVT::v4i32, Legal);
+ setOperationAction(ISD::SUB, EVT::v2i64, Legal);
+ setOperationAction(ISD::MUL, EVT::v8i16, Legal);
+ setOperationAction(ISD::FADD, EVT::v2f64, Legal);
+ setOperationAction(ISD::FSUB, EVT::v2f64, Legal);
+ setOperationAction(ISD::FMUL, EVT::v2f64, Legal);
+ setOperationAction(ISD::FDIV, EVT::v2f64, Legal);
+ setOperationAction(ISD::FSQRT, EVT::v2f64, Legal);
+ setOperationAction(ISD::FNEG, EVT::v2f64, Custom);
- setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
- setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
- setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
- setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v2f64, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v16i8, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v8i16, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v4i32, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v16i8, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v8i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f32, Custom);
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
- for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
- MVT VT = (MVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v2i64; ++i) {
+ EVT VT = (EVT::SimpleValueType)i;
// Do not attempt to custom lower non-power-of-2 vectors
if (!isPowerOf2_32(VT.getVectorNumElements()))
continue;
@@ -728,138 +728,138 @@
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
}
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v2f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v2i64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2f64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2f64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2f64, Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2i64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2i64, Custom);
}
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
- for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
- MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
- MVT VT = SVT;
+ for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v2i64; i++) {
+ EVT::SimpleValueType SVT = (EVT::SimpleValueType)i;
+ EVT VT = SVT;
// Do not attempt to promote non-128-bit vectors
if (!VT.is128BitVector()) {
continue;
}
setOperationAction(ISD::AND, SVT, Promote);
- AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
+ AddPromotedToType (ISD::AND, SVT, EVT::v2i64);
setOperationAction(ISD::OR, SVT, Promote);
- AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
+ AddPromotedToType (ISD::OR, SVT, EVT::v2i64);
setOperationAction(ISD::XOR, SVT, Promote);
- AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
+ AddPromotedToType (ISD::XOR, SVT, EVT::v2i64);
setOperationAction(ISD::LOAD, SVT, Promote);
- AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
+ AddPromotedToType (ISD::LOAD, SVT, EVT::v2i64);
setOperationAction(ISD::SELECT, SVT, Promote);
- AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
+ AddPromotedToType (ISD::SELECT, SVT, EVT::v2i64);
}
- setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ setTruncStoreAction(EVT::f64, EVT::f32, Expand);
// Custom lower v2i64 and v2f64 selects.
- setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
- setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
- setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
- setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
+ setOperationAction(ISD::LOAD, EVT::v2f64, Legal);
+ setOperationAction(ISD::LOAD, EVT::v2i64, Legal);
+ setOperationAction(ISD::SELECT, EVT::v2f64, Custom);
+ setOperationAction(ISD::SELECT, EVT::v2i64, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
- setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
+ setOperationAction(ISD::FP_TO_SINT, EVT::v4i32, Legal);
+ setOperationAction(ISD::SINT_TO_FP, EVT::v4i32, Legal);
if (!DisableMMX && Subtarget->hasMMX()) {
- setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
- setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, EVT::v2i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, EVT::v2i32, Custom);
}
}
if (Subtarget->hasSSE41()) {
// FIXME: Do we need to handle scalar-to-vector here?
- setOperationAction(ISD::MUL, MVT::v4i32, Legal);
+ setOperationAction(ISD::MUL, EVT::v4i32, Legal);
// i8 and i16 vectors are custom , because the source register and source
// source memory operand types are not the same width. f32 vectors are
// custom since the immediate controlling the insert encodes additional
// information.
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v16i8, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v16i8, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v8i16, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4i32, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f32, Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2i64, Legal);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2i64, Legal);
}
}
if (Subtarget->hasSSE42()) {
- setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v2i64, Custom);
}
if (!UseSoftFloat && Subtarget->hasAVX()) {
- addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
- addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
- addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
- addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
+ addRegisterClass(EVT::v8f32, X86::VR256RegisterClass);
+ addRegisterClass(EVT::v4f64, X86::VR256RegisterClass);
+ addRegisterClass(EVT::v8i32, X86::VR256RegisterClass);
+ addRegisterClass(EVT::v4i64, X86::VR256RegisterClass);
- setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
- setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
- setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
- setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
- setOperationAction(ISD::FADD, MVT::v8f32, Legal);
- setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
- setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
- setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
- setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
- setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
- //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
- //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
- //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
- //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
- //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
+ setOperationAction(ISD::LOAD, EVT::v8f32, Legal);
+ setOperationAction(ISD::LOAD, EVT::v8i32, Legal);
+ setOperationAction(ISD::LOAD, EVT::v4f64, Legal);
+ setOperationAction(ISD::LOAD, EVT::v4i64, Legal);
+ setOperationAction(ISD::FADD, EVT::v8f32, Legal);
+ setOperationAction(ISD::FSUB, EVT::v8f32, Legal);
+ setOperationAction(ISD::FMUL, EVT::v8f32, Legal);
+ setOperationAction(ISD::FDIV, EVT::v8f32, Legal);
+ setOperationAction(ISD::FSQRT, EVT::v8f32, Legal);
+ setOperationAction(ISD::FNEG, EVT::v8f32, Custom);
+ //setOperationAction(ISD::BUILD_VECTOR, EVT::v8f32, Custom);
+ //setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v8f32, Custom);
+ //setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v8f32, Custom);
+ //setOperationAction(ISD::SELECT, EVT::v8f32, Custom);
+ //setOperationAction(ISD::VSETCC, EVT::v8f32, Custom);
// Operations to consider commented out -v16i16 v32i8
- //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
- setOperationAction(ISD::ADD, MVT::v8i32, Custom);
- setOperationAction(ISD::ADD, MVT::v4i64, Custom);
- //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
- //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
- setOperationAction(ISD::SUB, MVT::v8i32, Custom);
- setOperationAction(ISD::SUB, MVT::v4i64, Custom);
- //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
- setOperationAction(ISD::FADD, MVT::v4f64, Legal);
- setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
- setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
- setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
- setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
- setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
+ //setOperationAction(ISD::ADD, EVT::v16i16, Legal);
+ setOperationAction(ISD::ADD, EVT::v8i32, Custom);
+ setOperationAction(ISD::ADD, EVT::v4i64, Custom);
+ //setOperationAction(ISD::SUB, EVT::v32i8, Legal);
+ //setOperationAction(ISD::SUB, EVT::v16i16, Legal);
+ setOperationAction(ISD::SUB, EVT::v8i32, Custom);
+ setOperationAction(ISD::SUB, EVT::v4i64, Custom);
+ //setOperationAction(ISD::MUL, EVT::v16i16, Legal);
+ setOperationAction(ISD::FADD, EVT::v4f64, Legal);
+ setOperationAction(ISD::FSUB, EVT::v4f64, Legal);
+ setOperationAction(ISD::FMUL, EVT::v4f64, Legal);
+ setOperationAction(ISD::FDIV, EVT::v4f64, Legal);
+ setOperationAction(ISD::FSQRT, EVT::v4f64, Legal);
+ setOperationAction(ISD::FNEG, EVT::v4f64, Custom);
- setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
- // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
- // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
- setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v4f64, Custom);
+ // setOperationAction(ISD::VSETCC, EVT::v32i8, Custom);
+ // setOperationAction(ISD::VSETCC, EVT::v16i16, Custom);
+ setOperationAction(ISD::VSETCC, EVT::v8i32, Custom);
- // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
- // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
- // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
+ // setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v32i8, Custom);
+ // setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v16i16, Custom);
+ // setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v16i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8f32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v4f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, EVT::v4i64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4f64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f64, Custom);
#if 0
// Not sure we want to do this since there are no 256-bit integer
@@ -867,8 +867,8 @@
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
// This includes 256-bit vectors
- for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
- MVT VT = (MVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v4i64; ++i) {
+ EVT VT = (EVT::SimpleValueType)i;
// Do not attempt to custom lower non-power-of-2 vectors
if (!isPowerOf2_32(VT.getVectorNumElements()))
@@ -880,8 +880,8 @@
}
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4i64, Custom);
}
#endif
@@ -891,42 +891,42 @@
// Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
// Including 256-bit vectors
- for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
- MVT VT = (MVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v4i64; i++) {
+ EVT VT = (EVT::SimpleValueType)i;
if (!VT.is256BitVector()) {
continue;
}
setOperationAction(ISD::AND, VT, Promote);
- AddPromotedToType (ISD::AND, VT, MVT::v4i64);
+ AddPromotedToType (ISD::AND, VT, EVT::v4i64);
setOperationAction(ISD::OR, VT, Promote);
- AddPromotedToType (ISD::OR, VT, MVT::v4i64);
+ AddPromotedToType (ISD::OR, VT, EVT::v4i64);
setOperationAction(ISD::XOR, VT, Promote);
- AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
+ AddPromotedToType (ISD::XOR, VT, EVT::v4i64);
setOperationAction(ISD::LOAD, VT, Promote);
- AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
+ AddPromotedToType (ISD::LOAD, VT, EVT::v4i64);
setOperationAction(ISD::SELECT, VT, Promote);
- AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
+ AddPromotedToType (ISD::SELECT, VT, EVT::v4i64);
}
- setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ setTruncStoreAction(EVT::f64, EVT::f32, Expand);
#endif
}
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
// Add/Sub/Mul with overflow operations are custom lowered.
- setOperationAction(ISD::SADDO, MVT::i32, Custom);
- setOperationAction(ISD::SADDO, MVT::i64, Custom);
- setOperationAction(ISD::UADDO, MVT::i32, Custom);
- setOperationAction(ISD::UADDO, MVT::i64, Custom);
- setOperationAction(ISD::SSUBO, MVT::i32, Custom);
- setOperationAction(ISD::SSUBO, MVT::i64, Custom);
- setOperationAction(ISD::USUBO, MVT::i32, Custom);
- setOperationAction(ISD::USUBO, MVT::i64, Custom);
- setOperationAction(ISD::SMULO, MVT::i32, Custom);
- setOperationAction(ISD::SMULO, MVT::i64, Custom);
+ setOperationAction(ISD::SADDO, EVT::i32, Custom);
+ setOperationAction(ISD::SADDO, EVT::i64, Custom);
+ setOperationAction(ISD::UADDO, EVT::i32, Custom);
+ setOperationAction(ISD::UADDO, EVT::i64, Custom);
+ setOperationAction(ISD::SSUBO, EVT::i32, Custom);
+ setOperationAction(ISD::SSUBO, EVT::i64, Custom);
+ setOperationAction(ISD::USUBO, EVT::i32, Custom);
+ setOperationAction(ISD::USUBO, EVT::i64, Custom);
+ setOperationAction(ISD::SMULO, EVT::i32, Custom);
+ setOperationAction(ISD::SMULO, EVT::i64, Custom);
if (!Subtarget->is64Bit()) {
// These libcalls are not available in 32-bit.
@@ -960,8 +960,8 @@
}
-MVT::SimpleValueType X86TargetLowering::getSetCCResultType(MVT VT) const {
- return MVT::i8;
+EVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
+ return EVT::i8;
}
@@ -1012,9 +1012,9 @@
/// getOptimalMemOpType - Returns the target specific optimal type for load
/// and store operations as a result of memset, memcpy, and memmove
-/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
+/// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
/// determining it.
-MVT
+EVT
X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr,
SelectionDAG &DAG) const {
@@ -1025,13 +1025,13 @@
bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
- return MVT::v4i32;
+ return EVT::v4i32;
if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
- return MVT::v4f32;
+ return EVT::v4f32;
}
if (Subtarget->is64Bit() && Size >= 8)
- return MVT::i64;
- return MVT::i32;
+ return EVT::i64;
+ return EVT::i32;
}
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
@@ -1083,7 +1083,7 @@
SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
- RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
+ RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), EVT::i16));
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -1098,7 +1098,7 @@
// If this is a copy from an xmm register to ST(0), use an FPExtend to
// change the value to the FP stack register class.
if (isScalarFPTypeInSSEReg(VA.getValVT()))
- ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f80, ValToCopy);
RetOps.push_back(ValToCopy);
// Don't emit a copytoreg.
continue;
@@ -1107,11 +1107,11 @@
// 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
// which is returned in RAX / RDX.
if (Subtarget->is64Bit()) {
- MVT ValVT = ValToCopy.getValueType();
+ EVT ValVT = ValToCopy.getValueType();
if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
- ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, ValToCopy);
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
- ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i64, ValToCopy);
}
}
@@ -1129,7 +1129,7 @@
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
unsigned Reg = FuncInfo->getSRetReturnReg();
if (!Reg) {
- Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
+ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
@@ -1145,7 +1145,7 @@
RetOps.push_back(Flag);
return DAG.getNode(X86ISD::RET_FLAG, dl,
- MVT::Other, &RetOps[0], RetOps.size());
+ EVT::Other, &RetOps[0], RetOps.size());
}
/// LowerCallResult - Lower the result values of a call into the
@@ -1168,10 +1168,10 @@
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
- MVT CopyVT = VA.getValVT();
+ EVT CopyVT = VA.getValVT();
// If this is x86-64, and we disabled SSE, we can't return FP values
- if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
+ if ((CopyVT == EVT::f32 || CopyVT == EVT::f64) &&
((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
llvm_report_error("SSE register return with SSE disabled");
}
@@ -1182,7 +1182,7 @@
if ((VA.getLocReg() == X86::ST0 ||
VA.getLocReg() == X86::ST1) &&
isScalarFPTypeInSSEReg(VA.getValVT())) {
- CopyVT = MVT::f80;
+ CopyVT = EVT::f80;
}
SDValue Val;
@@ -1190,13 +1190,13 @@
// For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
- MVT::v2i64, InFlag).getValue(1);
+ EVT::v2i64, InFlag).getValue(1);
Val = Chain.getValue(0);
- Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
- Val, DAG.getConstant(0, MVT::i64));
+ Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i64,
+ Val, DAG.getConstant(0, EVT::i64));
} else {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
- MVT::i64, InFlag).getValue(1);
+ EVT::i64, InFlag).getValue(1);
Val = Chain.getValue(0);
}
Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
@@ -1307,7 +1307,7 @@
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*AlwaysInline=*/true, NULL, 0, NULL, 0);
}
@@ -1384,15 +1384,15 @@
LastVal = VA.getValNo();
if (VA.isRegLoc()) {
- MVT RegVT = VA.getLocVT();
+ EVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = NULL;
- if (RegVT == MVT::i32)
+ if (RegVT == EVT::i32)
RC = X86::GR32RegisterClass;
- else if (Is64Bit && RegVT == MVT::i64)
+ else if (Is64Bit && RegVT == EVT::i64)
RC = X86::GR64RegisterClass;
- else if (RegVT == MVT::f32)
+ else if (RegVT == EVT::f32)
RC = X86::FR32RegisterClass;
- else if (RegVT == MVT::f64)
+ else if (RegVT == EVT::f64)
RC = X86::FR64RegisterClass;
else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
RC = X86::VR128RegisterClass;
@@ -1419,8 +1419,8 @@
if (VA.isExtInLoc()) {
// Handle MMX values passed in XMM regs.
if (RegVT.isVector()) {
- ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
- ArgValue, DAG.getConstant(0, MVT::i64));
+ ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i64,
+ ArgValue, DAG.getConstant(0, EVT::i64));
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
} else
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
@@ -1444,11 +1444,11 @@
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
unsigned Reg = FuncInfo->getSRetReturnReg();
if (!Reg) {
- Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
+ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Copy, Chain);
}
unsigned StackSize = CCInfo.getNextStackOffset();
@@ -1521,7 +1521,7 @@
for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
X86::GR64RegisterClass);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i64);
SDValue Store =
DAG.getStore(Val.getValue(1), dl, Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
@@ -1536,7 +1536,7 @@
for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
X86::VR128RegisterClass);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::v4f32);
SDValue Store =
DAG.getStore(Val.getValue(1), dl, Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
@@ -1545,7 +1545,7 @@
DAG.getIntPtrConstant(16));
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOps[0], MemOps.size());
}
}
@@ -1603,7 +1603,7 @@
if (!IsTailCall || FPDiff==0) return Chain;
// Adjust the Return address stack slot.
- MVT VT = getPointerTy();
+ EVT VT = getPointerTy();
OutRetAddr = getReturnAddressFrameIndex(DAG);
// Load the "old" Return address.
@@ -1623,7 +1623,7 @@
int SlotSize = Is64Bit ? 8 : 4;
int NewReturnAddrFI =
MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
- MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
+ EVT VT = Is64Bit ? EVT::i64 : EVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
@@ -1687,7 +1687,7 @@
// of tail call optimization arguments are handle later.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- MVT RegVT = VA.getLocVT();
+ EVT RegVT = VA.getLocVT();
SDValue Arg = Outs[i].Val;
ISD::ArgFlagsTy Flags = Outs[i].Flags;
bool isByVal = Flags.isByVal();
@@ -1705,9 +1705,9 @@
case CCValAssign::AExt:
if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
// Special case: passing MMX values in XMM registers.
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
- Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
- Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, Arg);
+ Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i64, Arg);
+ Arg = getMOVL(DAG, dl, EVT::v2i64, DAG.getUNDEF(EVT::v2i64), Arg);
} else
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
break;
@@ -1740,7 +1740,7 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
@@ -1805,7 +1805,7 @@
&& "SSE registers cannot be used when SSE is disabled");
Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
- DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
+ DAG.getConstant(NumXMMRegs, EVT::i8), InFlag);
InFlag = Chain.getValue(1);
}
@@ -1858,7 +1858,7 @@
}
if (!MemOpChains2.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains2[0], MemOpChains2.size());
// Copy arguments to their registers.
@@ -1933,7 +1933,7 @@
}
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
SmallVector<SDValue, 8> Ops;
if (isTailCall) {
@@ -1946,7 +1946,7 @@
Ops.push_back(Callee);
if (isTailCall)
- Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
+ Ops.push_back(DAG.getConstant(FPDiff, EVT::i32));
// Add argument registers to the end of the list so that they are known live
// into the call.
@@ -1960,7 +1960,7 @@
// Add an implicit use of AL for x86 vararg functions.
if (Is64Bit && isVarArg)
- Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
+ Ops.push_back(DAG.getRegister(X86::AL, EVT::i8));
if (InFlag.getNode())
Ops.push_back(InFlag);
@@ -2277,10 +2277,10 @@
/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
/// the second operand.
-static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
- if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
+static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
+ if (VT == EVT::v4f32 || VT == EVT::v4i32 || VT == EVT::v4i16)
return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
- if (VT == MVT::v2f64 || VT == MVT::v2i64)
+ if (VT == EVT::v2f64 || VT == EVT::v2i64)
return (Mask[0] < 2 && Mask[1] < 2);
return false;
}
@@ -2293,8 +2293,8 @@
/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
/// is suitable for input to PSHUFHW.
-static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
- if (VT != MVT::v8i16)
+static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
+ if (VT != EVT::v8i16)
return false;
// Lower quadword copied in order or undef.
@@ -2318,8 +2318,8 @@
/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
/// is suitable for input to PSHUFLW.
-static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
- if (VT != MVT::v8i16)
+static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
+ if (VT != EVT::v8i16)
return false;
// Upper quadword copied in order.
@@ -2343,7 +2343,7 @@
/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to SHUFP*.
-static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
int NumElems = VT.getVectorNumElements();
if (NumElems != 2 && NumElems != 4)
return false;
@@ -2369,7 +2369,7 @@
/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
/// half elements to come from vector 1 (which would equal the dest.) and
/// the upper half to come from vector 2.
-static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
int NumElems = VT.getVectorNumElements();
if (NumElems != 2 && NumElems != 4)
@@ -2460,7 +2460,7 @@
/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to UNPCKL.
-static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
+static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
bool V2IsSplat = false) {
int NumElts = VT.getVectorNumElements();
if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
@@ -2490,7 +2490,7 @@
/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to UNPCKH.
-static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT,
+static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
bool V2IsSplat = false) {
int NumElts = VT.getVectorNumElements();
if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
@@ -2521,7 +2521,7 @@
/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
/// <0, 0, 1, 1>
-static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
int NumElems = VT.getVectorNumElements();
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
return false;
@@ -2546,7 +2546,7 @@
/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
/// <2, 2, 3, 3>
-static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
int NumElems = VT.getVectorNumElements();
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
return false;
@@ -2571,7 +2571,7 @@
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element.
-static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
if (VT.getVectorElementType().getSizeInBits() < 32)
return false;
@@ -2596,7 +2596,7 @@
/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
/// of what x86 movss want. X86 movs requires the lowest element to be lowest
/// element of vector 2 and the other elements to come from vector 1 in order.
-static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
+static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
bool V2IsSplat = false, bool V2IsUndef = false) {
int NumOps = VT.getVectorNumElements();
if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
@@ -2751,7 +2751,7 @@
/// their permute mask.
static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
SelectionDAG &DAG) {
- MVT VT = SVOp->getValueType(0);
+ EVT VT = SVOp->getValueType(0);
unsigned NumElems = VT.getVectorNumElements();
SmallVector<int, 8> MaskVec;
@@ -2770,7 +2770,7 @@
/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
/// the two vector operands have swapped position.
-static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
+static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
unsigned NumElems = VT.getVectorNumElements();
for (unsigned i = 0; i != NumElems; ++i) {
int idx = Mask[i];
@@ -2883,7 +2883,7 @@
/// getZeroVector - Returns a vector of specified type with all zero elements.
///
-static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
+static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
@@ -2891,31 +2891,31 @@
// type. This ensures they get CSE'd.
SDValue Vec;
if (VT.getSizeInBits() == 64) { // MMX
- SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstant(0, EVT::i32);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
} else if (HasSSE2) { // SSE2
- SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstant(0, EVT::i32);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
} else { // SSE1
- SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstantFP(+0.0, EVT::f32);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4f32, Cst, Cst, Cst, Cst);
}
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
/// getOnesVector - Returns a vector of specified type with all bits set.
///
-static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
+static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
- SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
+ SDValue Cst = DAG.getTargetConstant(~0U, EVT::i32);
SDValue Vec;
if (VT.getSizeInBits() == 64) // MMX
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
else // SSE
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2923,7 +2923,7 @@
/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
/// that point to V2 points to its first element.
static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
- MVT VT = SVOp->getValueType(0);
+ EVT VT = SVOp->getValueType(0);
unsigned NumElems = VT.getVectorNumElements();
bool Changed = false;
@@ -2944,7 +2944,7 @@
/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
/// operation of specified width.
-static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2) {
unsigned NumElems = VT.getVectorNumElements();
SmallVector<int, 8> Mask;
@@ -2955,7 +2955,7 @@
}
/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
-static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2) {
unsigned NumElems = VT.getVectorNumElements();
SmallVector<int, 8> Mask;
@@ -2967,7 +2967,7 @@
}
/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
-static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2) {
unsigned NumElems = VT.getVectorNumElements();
unsigned Half = NumElems/2;
@@ -2985,8 +2985,8 @@
if (SV->getValueType(0).getVectorNumElements() <= 4)
return SDValue(SV, 0);
- MVT PVT = MVT::v4f32;
- MVT VT = SV->getValueType(0);
+ EVT PVT = EVT::v4f32;
+ EVT VT = SV->getValueType(0);
DebugLoc dl = SV->getDebugLoc();
SDValue V1 = SV->getOperand(0);
int NumElems = VT.getVectorNumElements();
@@ -3017,7 +3017,7 @@
static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
bool isZero, bool HasSSE2,
SelectionDAG &DAG) {
- MVT VT = V2.getValueType();
+ EVT VT = V2.getValueType();
SDValue V1 = isZero
? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
unsigned NumElems = VT.getVectorNumElements();
@@ -3105,9 +3105,9 @@
bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
if (ThisIsNonZero && First) {
if (NumZero)
- V = getZeroVector(MVT::v8i16, true, DAG, dl);
+ V = getZeroVector(EVT::v8i16, true, DAG, dl);
else
- V = DAG.getUNDEF(MVT::v8i16);
+ V = DAG.getUNDEF(EVT::v8i16);
First = false;
}
@@ -3116,24 +3116,24 @@
bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
if (LastIsNonZero) {
LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
- MVT::i16, Op.getOperand(i-1));
+ EVT::i16, Op.getOperand(i-1));
}
if (ThisIsNonZero) {
- ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
- ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
- ThisElt, DAG.getConstant(8, MVT::i8));
+ ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, Op.getOperand(i));
+ ThisElt = DAG.getNode(ISD::SHL, dl, EVT::i16,
+ ThisElt, DAG.getConstant(8, EVT::i8));
if (LastIsNonZero)
- ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
+ ThisElt = DAG.getNode(ISD::OR, dl, EVT::i16, ThisElt, LastElt);
} else
ThisElt = LastElt;
if (ThisElt.getNode())
- V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
+ V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, V, ThisElt,
DAG.getIntPtrConstant(i/2));
}
}
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V);
}
/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
@@ -3152,13 +3152,13 @@
if (isNonZero) {
if (First) {
if (NumZero)
- V = getZeroVector(MVT::v8i16, true, DAG, dl);
+ V = getZeroVector(EVT::v8i16, true, DAG, dl);
else
- V = DAG.getUNDEF(MVT::v8i16);
+ V = DAG.getUNDEF(EVT::v8i16);
First = false;
}
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
- MVT::v8i16, V, Op.getOperand(i),
+ EVT::v8i16, V, Op.getOperand(i),
DAG.getIntPtrConstant(i));
}
}
@@ -3168,11 +3168,11 @@
/// getVShift - Return a vector logical shift node.
///
-static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
+static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
unsigned NumBits, SelectionDAG &DAG,
const TargetLowering &TLI, DebugLoc dl) {
bool isMMX = VT.getSizeInBits() == 64;
- MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
+ EVT ShVT = isMMX ? EVT::v1i64 : EVT::v2i64;
unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
@@ -3189,7 +3189,7 @@
// Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
// 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
// eliminated on x86-32 hosts.
- if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
+ if (Op.getValueType() == EVT::v4i32 || Op.getValueType() == EVT::v2i32)
return Op;
if (ISD::isBuildVectorAllOnes(Op.getNode()))
@@ -3197,9 +3197,9 @@
return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
}
- MVT VT = Op.getValueType();
- MVT EVT = VT.getVectorElementType();
- unsigned EVTBits = EVT.getSizeInBits();
+ EVT VT = Op.getValueType();
+ EVT ExtVT = VT.getVectorElementType();
+ unsigned EVTBits = ExtVT.getSizeInBits();
unsigned NumElems = Op.getNumOperands();
unsigned NumZero = 0;
@@ -3238,16 +3238,16 @@
// insertion that way. Only do this if the value is non-constant or if the
// value is a constant being inserted into element 0. It is cheaper to do
// a constant pool load than it is to do a movd + shuffle.
- if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
+ if (ExtVT == EVT::i64 && !Subtarget->is64Bit() &&
(!IsAllConstants || Idx == 0)) {
if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
// Handle MMX and SSE both.
- MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
- unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
+ EVT VecVT = VT == EVT::v2i64 ? EVT::v4i32 : EVT::v2i32;
+ unsigned VecElts = VT == EVT::v2i64 ? 4 : 2;
// Truncate the value (which may itself be a constant) to i32, and
// convert it to a vector with movd (S2V+shuffle to zero extend).
- Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
+ Item = DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, Item);
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasSSE2(), DAG);
@@ -3274,15 +3274,15 @@
if (Idx == 0) {
if (NumZero == 0) {
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
- } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 ||
- (EVT == MVT::i64 && Subtarget->is64Bit())) {
+ } else if (ExtVT == EVT::i32 || ExtVT == EVT::f32 || ExtVT == EVT::f64 ||
+ (ExtVT == EVT::i64 && Subtarget->is64Bit())) {
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
// Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
DAG);
- } else if (EVT == MVT::i16 || EVT == MVT::i8) {
- Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
- MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
+ } else if (ExtVT == EVT::i16 || ExtVT == EVT::i8) {
+ Item = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Item);
+ EVT MiddleVT = VT.getSizeInBits() == 64 ? EVT::v2i32 : EVT::v4i32;
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasSSE2(), DAG);
@@ -3508,10 +3508,10 @@
SmallVector<int, 8> MaskV;
MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
- NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
- NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
+ NewV = DAG.getVectorShuffle(EVT::v2i64, dl,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, V1),
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, V2), &MaskV[0]);
+ NewV = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, NewV);
// Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
// source words for the shuffle, to aid later transformations.
@@ -3548,8 +3548,8 @@
// If we've eliminated the use of V2, and the new mask is a pshuflw or
// pshufhw, that's as cheap as it gets. Return the new shuffle.
if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
- return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
- DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
+ return DAG.getVectorShuffle(EVT::v8i16, dl, NewV,
+ DAG.getUNDEF(EVT::v8i16), &MaskVals[0]);
}
}
@@ -3567,19 +3567,19 @@
for (unsigned i = 0; i != 8; ++i) {
int EltIdx = MaskVals[i] * 2;
if (TwoInputs && (EltIdx >= 16)) {
- pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
- pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
- pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx+1, EVT::i8));
}
- V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
- V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
+ V1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V1);
+ V1 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V1,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- MVT::v16i8, &pshufbMask[0], 16));
+ EVT::v16i8, &pshufbMask[0], 16));
if (!TwoInputs)
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1);
// Calculate the shuffle mask for the second input, shuffle it, and
// OR it with the first shuffled input.
@@ -3587,19 +3587,19 @@
for (unsigned i = 0; i != 8; ++i) {
int EltIdx = MaskVals[i] * 2;
if (EltIdx < 16) {
- pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
- pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
- pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx - 16, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx - 15, EVT::i8));
}
- V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
- V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
+ V2 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V2);
+ V2 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V2,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- MVT::v16i8, &pshufbMask[0], 16));
- V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
+ EVT::v16i8, &pshufbMask[0], 16));
+ V1 = DAG.getNode(ISD::OR, dl, EVT::v16i8, V1, V2);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1);
}
// If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
@@ -3621,7 +3621,7 @@
}
for (unsigned i = 4; i != 8; ++i)
MaskV.push_back(i);
- NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
+ NewV = DAG.getVectorShuffle(EVT::v8i16, dl, NewV, DAG.getUNDEF(EVT::v8i16),
&MaskV[0]);
}
@@ -3643,7 +3643,7 @@
MaskV.push_back(-1);
}
}
- NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
+ NewV = DAG.getVectorShuffle(EVT::v8i16, dl, NewV, DAG.getUNDEF(EVT::v8i16),
&MaskV[0]);
}
@@ -3665,11 +3665,11 @@
if (EltIdx < 0)
continue;
SDValue ExtOp = (EltIdx < 8)
- ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
+ ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, V1,
DAG.getIntPtrConstant(EltIdx))
- : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
+ : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, V2,
DAG.getIntPtrConstant(EltIdx - 8));
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, ExtOp,
DAG.getIntPtrConstant(i));
}
return NewV;
@@ -3718,18 +3718,18 @@
for (unsigned i = 0; i != 16; ++i) {
int EltIdx = MaskVals[i];
if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
- pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx, EVT::i8));
}
// If all the elements are from V2, assign it to V1 and return after
// building the first pshufb.
if (V2Only)
V1 = V2;
- V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
+ V1 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V1,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- MVT::v16i8, &pshufbMask[0], 16));
+ EVT::v16i8, &pshufbMask[0], 16));
if (!TwoInputs)
return V1;
@@ -3739,22 +3739,22 @@
for (unsigned i = 0; i != 16; ++i) {
int EltIdx = MaskVals[i];
if (EltIdx < 16) {
- pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx - 16, EVT::i8));
}
- V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
+ V2 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V2,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- MVT::v16i8, &pshufbMask[0], 16));
- return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
+ EVT::v16i8, &pshufbMask[0], 16));
+ return DAG.getNode(ISD::OR, dl, EVT::v16i8, V1, V2);
}
// No SSSE3 - Calculate in place words and then fix all out of place words
// With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
// the 16 different words that comprise the two doublequadword input vectors.
- V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
- V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
+ V1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1);
+ V2 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V2);
SDValue NewV = V2Only ? V2 : V1;
for (int i = 0; i != 8; ++i) {
int Elt0 = MaskVals[i*2];
@@ -3777,9 +3777,9 @@
// If Elt0 and Elt1 are defined, are consecutive, and can be load
// using a single extract together, load it and store it.
if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
- InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
+ InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, Elt1Src,
DAG.getIntPtrConstant(Elt1 / 2));
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, InsElt,
DAG.getIntPtrConstant(i));
continue;
}
@@ -3788,35 +3788,35 @@
// source byte is not also odd, shift the extracted word left 8 bits
// otherwise clear the bottom 8 bits if we need to do an or.
if (Elt1 >= 0) {
- InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
+ InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, Elt1Src,
DAG.getIntPtrConstant(Elt1 / 2));
if ((Elt1 & 1) == 0)
- InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
+ InsElt = DAG.getNode(ISD::SHL, dl, EVT::i16, InsElt,
DAG.getConstant(8, TLI.getShiftAmountTy()));
else if (Elt0 >= 0)
- InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
- DAG.getConstant(0xFF00, MVT::i16));
+ InsElt = DAG.getNode(ISD::AND, dl, EVT::i16, InsElt,
+ DAG.getConstant(0xFF00, EVT::i16));
}
// If Elt0 is defined, extract it from the appropriate source. If the
// source byte is not also even, shift the extracted word right 8 bits. If
// Elt1 was also defined, OR the extracted values together before
// inserting them in the result.
if (Elt0 >= 0) {
- SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
+ SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16,
Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
if ((Elt0 & 1) != 0)
- InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
+ InsElt0 = DAG.getNode(ISD::SRL, dl, EVT::i16, InsElt0,
DAG.getConstant(8, TLI.getShiftAmountTy()));
else if (Elt1 >= 0)
- InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
- DAG.getConstant(0x00FF, MVT::i16));
- InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
+ InsElt0 = DAG.getNode(ISD::AND, dl, EVT::i16, InsElt0,
+ DAG.getConstant(0x00FF, EVT::i16));
+ InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, EVT::i16, InsElt, InsElt0)
: InsElt0;
}
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, InsElt,
DAG.getIntPtrConstant(i));
}
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, NewV);
}
/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
@@ -3828,27 +3828,27 @@
SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
SelectionDAG &DAG,
TargetLowering &TLI, DebugLoc dl) {
- MVT VT = SVOp->getValueType(0);
+ EVT VT = SVOp->getValueType(0);
SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1);
unsigned NumElems = VT.getVectorNumElements();
unsigned NewWidth = (NumElems == 4) ? 2 : 4;
- MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
- MVT MaskEltVT = MaskVT.getVectorElementType();
- MVT NewVT = MaskVT;
+ EVT MaskVT = EVT::getIntVectorWithNumElements(NewWidth);
+ EVT MaskEltVT = MaskVT.getVectorElementType();
+ EVT NewVT = MaskVT;
switch (VT.getSimpleVT()) {
default: assert(false && "Unexpected!");
- case MVT::v4f32: NewVT = MVT::v2f64; break;
- case MVT::v4i32: NewVT = MVT::v2i64; break;
- case MVT::v8i16: NewVT = MVT::v4i32; break;
- case MVT::v16i8: NewVT = MVT::v4i32; break;
+ case EVT::v4f32: NewVT = EVT::v2f64; break;
+ case EVT::v4i32: NewVT = EVT::v2i64; break;
+ case EVT::v8i16: NewVT = EVT::v4i32; break;
+ case EVT::v16i8: NewVT = EVT::v4i32; break;
}
if (NewWidth == 2) {
if (VT.isInteger())
- NewVT = MVT::v2i64;
+ NewVT = EVT::v2i64;
else
- NewVT = MVT::v2f64;
+ NewVT = EVT::v2f64;
}
int Scale = NumElems / NewWidth;
SmallVector<int, 8> MaskVec;
@@ -3876,23 +3876,23 @@
/// getVZextMovL - Return a zero-extending vector move low node.
///
-static SDValue getVZextMovL(MVT VT, MVT OpVT,
+static SDValue getVZextMovL(EVT VT, EVT OpVT,
SDValue SrcOp, SelectionDAG &DAG,
const X86Subtarget *Subtarget, DebugLoc dl) {
- if (VT == MVT::v2f64 || VT == MVT::v4f32) {
+ if (VT == EVT::v2f64 || VT == EVT::v4f32) {
LoadSDNode *LD = NULL;
if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
LD = dyn_cast<LoadSDNode>(SrcOp);
if (!LD) {
// movssrr and movsdrr do not clear top bits. Try to use movd, movq
// instead.
- MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
- if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
+ EVT EVT = (OpVT == EVT::v2f64) ? EVT::i64 : EVT::i32;
+ if ((EVT != EVT::i64 || Subtarget->is64Bit()) &&
SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
// PR2108
- OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
+ OpVT = (OpVT == EVT::v2f64) ? EVT::v2i64 : EVT::v4i32;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
@@ -3916,7 +3916,7 @@
SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1);
DebugLoc dl = SVOp->getDebugLoc();
- MVT VT = SVOp->getValueType(0);
+ EVT VT = SVOp->getValueType(0);
SmallVector<std::pair<int, int>, 8> Locs;
Locs.resize(4);
@@ -4063,7 +4063,7 @@
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
unsigned NumElems = VT.getVectorNumElements();
bool isMMX = VT.getSizeInBits() == 64;
@@ -4084,12 +4084,12 @@
// If the shuffle can be profitably rewritten as a narrower shuffle, then
// do it!
- if (VT == MVT::v8i16 || VT == MVT::v16i8) {
+ if (VT == EVT::v8i16 || VT == EVT::v16i8) {
SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
if (NewOp.getNode())
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
LowerVECTOR_SHUFFLE(NewOp, DAG));
- } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
+ } else if ((VT == EVT::v4i32 || (VT == EVT::v4f32 && Subtarget->hasSSE2()))) {
// FIXME: Figure out a cleaner way to do this.
// Try to make use of movq to zero out the top part.
if (ISD::isBuildVectorAllZeros(V2.getNode())) {
@@ -4119,7 +4119,7 @@
if (isShift && ShVal.hasOneUse()) {
// If the shifted value has multiple uses, it may be cheaper to use
// v_set0 + movlhps or movhlps, etc.
- MVT EVT = VT.getVectorElementType();
+ EVT EVT = VT.getVectorElementType();
ShAmt *= EVT.getSizeInBits();
return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
}
@@ -4147,7 +4147,7 @@
if (isShift) {
// No better options. Use a vshl / vsrl.
- MVT EVT = VT.getVectorElementType();
+ EVT EVT = VT.getVectorElementType();
ShAmt *= EVT.getSizeInBits();
return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
}
@@ -4225,13 +4225,13 @@
return Op;
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
- if (VT == MVT::v8i16) {
+ if (VT == EVT::v8i16) {
SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
if (NewOp.getNode())
return NewOp;
}
- if (VT == MVT::v16i8) {
+ if (VT == EVT::v16i8) {
SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
if (NewOp.getNode())
return NewOp;
@@ -4247,30 +4247,30 @@
SDValue
X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
if (VT.getSizeInBits() == 8) {
- SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, EVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
} else if (VT.getSizeInBits() == 16) {
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
// If Idx is 0, it's cheaper to do a move instead of a pextrw.
if (Idx == 0)
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i16,
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32,
DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::v4i32,
+ EVT::v4i32,
Op.getOperand(0)),
Op.getOperand(1)));
- SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
- } else if (VT == MVT::f32) {
+ } else if (VT == EVT::f32) {
// EXTRACTPS outputs to a GPR32 register which will require a movd to copy
// the result back to FR32 register. It's only worth matching if the
// result has a single use which is a store or a bitcast to i32. And in
@@ -4283,14 +4283,14 @@
(isa<ConstantSDNode>(Op.getOperand(1)) &&
cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
(User->getOpcode() != ISD::BIT_CONVERT ||
- User->getValueType(0) != MVT::i32))
+ User->getValueType(0) != EVT::i32))
return SDValue();
- SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
+ SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4i32,
Op.getOperand(0)),
Op.getOperand(1));
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
- } else if (VT == MVT::i32) {
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Extract);
+ } else if (VT == EVT::i32) {
// ExtractPS works with constant index.
if (isa<ConstantSDNode>(Op.getOperand(1)))
return Op;
@@ -4310,20 +4310,20 @@
return Res;
}
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
// TODO: handle v16i8.
if (VT.getSizeInBits() == 16) {
SDValue Vec = Op.getOperand(0);
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Idx == 0)
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i16,
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32,
DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::v4i32, Vec),
+ EVT::v4i32, Vec),
Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result.
- MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
+ EVT EVT = (EVT::SimpleValueType)(VT.getSimpleVT()+1);
SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
Op.getOperand(0), Op.getOperand(1));
SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
@@ -4336,7 +4336,7 @@
// SHUFPS the element to the lowest double word, then movss.
int Mask[4] = { Idx, -1, -1, -1 };
- MVT VVT = Op.getOperand(0).getValueType();
+ EVT VVT = Op.getOperand(0).getValueType();
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
DAG.getUNDEF(VVT), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
@@ -4353,7 +4353,7 @@
// Note if the lower 64 bits of the result of the UNPCKHPD is then stored
// to a f64mem, the whole operation is folded into a single MOVHPDmr.
int Mask[2] = { 1, -1 };
- MVT VVT = Op.getOperand(0).getValueType();
+ EVT VVT = Op.getOperand(0).getValueType();
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
DAG.getUNDEF(VVT), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
@@ -4365,8 +4365,8 @@
SDValue
X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
- MVT VT = Op.getValueType();
- MVT EVT = VT.getVectorElementType();
+ EVT VT = Op.getValueType();
+ EVT EVT = VT.getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
SDValue N0 = Op.getOperand(0);
@@ -4379,12 +4379,12 @@
: X86ISD::PINSRW;
// Transform it so it match pinsr{b,w} which expects a GR32 as its second
// argument.
- if (N1.getValueType() != MVT::i32)
- N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
- if (N2.getValueType() != MVT::i32)
+ if (N1.getValueType() != EVT::i32)
+ N1 = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, N1);
+ if (N2.getValueType() != EVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
return DAG.getNode(Opc, dl, VT, N0, N1, N2);
- } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
+ } else if (EVT == EVT::f32 && isa<ConstantSDNode>(N2)) {
// Bits [7:6] of the constant are the source select. This will always be
// zero here. The DAG Combiner may combine an extract_elt index into these
// bits. For example (insert (extract, 3), 2) could be matched by putting
@@ -4395,9 +4395,9 @@
// combine either bitwise AND or insert of float 0.0 to set these bits.
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
// Create this as a scalar to vector..
- N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
+ N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4f32, N1);
return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
- } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
+ } else if (EVT == EVT::i32 && isa<ConstantSDNode>(N2)) {
// PINSR* works with constant index.
return Op;
}
@@ -4406,13 +4406,13 @@
SDValue
X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
- MVT EVT = VT.getVectorElementType();
+ EVT VT = Op.getValueType();
+ EVT EVT = VT.getVectorElementType();
if (Subtarget->hasSSE41())
return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
- if (EVT == MVT::i8)
+ if (EVT == EVT::i8)
return SDValue();
DebugLoc dl = Op.getDebugLoc();
@@ -4423,9 +4423,9 @@
if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
// Transform it so it match pinsrw which expects a 16-bit value in a GR32
// as its second argument.
- if (N1.getValueType() != MVT::i32)
- N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
- if (N2.getValueType() != MVT::i32)
+ if (N1.getValueType() != EVT::i32)
+ N1 = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, N1);
+ if (N2.getValueType() != EVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
}
@@ -4435,22 +4435,22 @@
SDValue
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- if (Op.getValueType() == MVT::v2f32)
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
+ if (Op.getValueType() == EVT::v2f32)
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f32,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32,
Op.getOperand(0))));
- if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
- return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
+ if (Op.getValueType() == EVT::v1i64 && Op.getOperand(0).getValueType() == EVT::i64)
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v1i64, Op.getOperand(0));
- SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
- MVT VT = MVT::v2i32;
+ SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, Op.getOperand(0));
+ EVT VT = EVT::v2i32;
switch (Op.getValueType().getSimpleVT()) {
default: break;
- case MVT::v16i8:
- case MVT::v8i16:
- VT = MVT::v4i32;
+ case EVT::v16i8:
+ case EVT::v8i16:
+ VT = EVT::v4i32;
break;
}
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
@@ -4623,9 +4623,9 @@
static SDValue
GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
- SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg,
+ SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
unsigned char OperandFlags) {
- SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
DebugLoc dl = GA->getDebugLoc();
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
GA->getValueType(0),
@@ -4645,7 +4645,7 @@
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
static SDValue
LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
- const MVT PtrVT) {
+ const EVT PtrVT) {
SDValue InFlag;
DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
@@ -4660,7 +4660,7 @@
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
static SDValue
LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
- const MVT PtrVT) {
+ const EVT PtrVT) {
return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
X86::RAX, X86II::MO_TLSGD);
}
@@ -4668,14 +4668,14 @@
// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
// "local exec" model.
static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
- const MVT PtrVT, TLSModel::Model model,
+ const EVT PtrVT, TLSModel::Model model,
bool is64Bit) {
DebugLoc dl = GA->getDebugLoc();
// Get the Thread Pointer
SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
DebugLoc::getUnknownLoc(), PtrVT,
DAG.getRegister(is64Bit? X86::FS : X86::GS,
- MVT::i32));
+ EVT::i32));
SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
NULL, 0);
@@ -4749,7 +4749,7 @@
/// take a 2 x i32 value to shift plus a shift amount.
SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits();
DebugLoc dl = Op.getDebugLoc();
bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
@@ -4757,7 +4757,7 @@
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
- DAG.getConstant(VTBits - 1, MVT::i8))
+ DAG.getConstant(VTBits - 1, EVT::i8))
: DAG.getConstant(0, VT);
SDValue Tmp2, Tmp3;
@@ -4769,13 +4769,13 @@
Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
}
- SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
- DAG.getConstant(VTBits, MVT::i8));
+ SDValue AndNode = DAG.getNode(ISD::AND, dl, EVT::i8, ShAmt,
+ DAG.getConstant(VTBits, EVT::i8));
SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
- AndNode, DAG.getConstant(0, MVT::i8));
+ AndNode, DAG.getConstant(0, EVT::i8));
SDValue Hi, Lo;
- SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+ SDValue CC = DAG.getConstant(X86::COND_NE, EVT::i8);
SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
@@ -4792,23 +4792,23 @@
}
SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
- MVT SrcVT = Op.getOperand(0).getValueType();
+ EVT SrcVT = Op.getOperand(0).getValueType();
if (SrcVT.isVector()) {
- if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
+ if (SrcVT == EVT::v2i32 && Op.getValueType() == EVT::v2f64) {
return Op;
}
return SDValue();
}
- assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
+ assert(SrcVT.getSimpleVT() <= EVT::i64 && SrcVT.getSimpleVT() >= EVT::i16 &&
"Unknown SINT_TO_FP to lower!");
// These are really Legal; return the operand so the caller accepts it as
// Legal.
- if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
+ if (SrcVT == EVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
return Op;
- if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
+ if (SrcVT == EVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
Subtarget->is64Bit()) {
return Op;
}
@@ -4824,7 +4824,7 @@
return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
}
-SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
+SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
SDValue StackSlot,
SelectionDAG &DAG) {
// Build the FILD
@@ -4832,9 +4832,9 @@
SDVTList Tys;
bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
if (useSSE)
- Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
+ Tys = DAG.getVTList(EVT::f64, EVT::Other, EVT::Flag);
else
- Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
+ Tys = DAG.getVTList(Op.getValueType(), EVT::Other);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(StackSlot);
@@ -4852,7 +4852,7 @@
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- Tys = DAG.getVTList(MVT::Other);
+ Tys = DAG.getVTList(EVT::Other);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Result);
@@ -4923,31 +4923,31 @@
Constant *C1 = ConstantVector::get(CV1);
SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
- SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(1)));
- SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(0)));
- SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
- SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
+ SDValue Unpck1 = getUnpackl(DAG, dl, EVT::v4i32, XR1, XR2);
+ SDValue CLod0 = DAG.getLoad(EVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
- SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
- SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
+ SDValue Unpck2 = getUnpackl(DAG, dl, EVT::v4i32, Unpck1, CLod0);
+ SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Unpck2);
+ SDValue CLod1 = DAG.getLoad(EVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::v2f64, XR2F, CLod1);
// Add the halves; easiest way is to swap them into another reg first.
int ShufMask[2] = { 1, -1 };
- SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
- DAG.getUNDEF(MVT::v2f64), ShufMask);
- SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
+ SDValue Shuf = DAG.getVectorShuffle(EVT::v2f64, dl, Sub,
+ DAG.getUNDEF(EVT::v2f64), ShufMask);
+ SDValue Add = DAG.getNode(ISD::FADD, dl, EVT::v2f64, Shuf, Sub);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Add,
DAG.getIntPtrConstant(0));
}
@@ -4956,40 +4956,40 @@
DebugLoc dl = Op.getDebugLoc();
// FP constant to bias correct the final result.
SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
- MVT::f64);
+ EVT::f64);
// Load the 32-bit value into an XMM register.
- SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(0)));
- Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
+ Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Load),
DAG.getIntPtrConstant(0));
// Or the load with the bias.
- SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
+ SDValue Or = DAG.getNode(ISD::OR, dl, EVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
- MVT::v2f64, Load)),
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
+ EVT::v2f64, Load)),
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
- MVT::v2f64, Bias)));
- Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
+ EVT::v2f64, Bias)));
+ Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Or),
DAG.getIntPtrConstant(0));
// Subtract the bias.
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Or, Bias);
// Handle final rounding.
- MVT DestVT = Op.getValueType();
+ EVT DestVT = Op.getValueType();
- if (DestVT.bitsLT(MVT::f64)) {
+ if (DestVT.bitsLT(EVT::f64)) {
return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
- } else if (DestVT.bitsGT(MVT::f64)) {
+ } else if (DestVT.bitsGT(EVT::f64)) {
return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
@@ -5007,52 +5007,52 @@
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
- MVT SrcVT = N0.getValueType();
- if (SrcVT == MVT::i64) {
+ EVT SrcVT = N0.getValueType();
+ if (SrcVT == EVT::i64) {
// We only handle SSE2 f64 target here; caller can expand the rest.
- if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
+ if (Op.getValueType() != EVT::f64 || !X86ScalarSSEf64)
return SDValue();
return LowerUINT_TO_FP_i64(Op, DAG);
- } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
+ } else if (SrcVT == EVT::i32 && X86ScalarSSEf64) {
return LowerUINT_TO_FP_i32(Op, DAG);
}
- assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
+ assert(SrcVT == EVT::i32 && "Unknown UINT_TO_FP to lower!");
// Make a 64-bit buffer, and use it to build an FILD.
- SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
+ SDValue StackSlot = DAG.CreateStackTemporary(EVT::i64);
SDValue WordOff = DAG.getConstant(4, getPointerTy());
SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
getPointerTy(), StackSlot, WordOff);
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
StackSlot, NULL, 0);
- SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
+ SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, EVT::i32),
OffsetSlot, NULL, 0);
- return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
+ return BuildFILD(Op, EVT::i64, Store2, StackSlot, DAG);
}
std::pair<SDValue,SDValue> X86TargetLowering::
FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
DebugLoc dl = Op.getDebugLoc();
- MVT DstTy = Op.getValueType();
+ EVT DstTy = Op.getValueType();
if (!IsSigned) {
- assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
- DstTy = MVT::i64;
+ assert(DstTy == EVT::i32 && "Unexpected FP_TO_UINT");
+ DstTy = EVT::i64;
}
- assert(DstTy.getSimpleVT() <= MVT::i64 &&
- DstTy.getSimpleVT() >= MVT::i16 &&
+ assert(DstTy.getSimpleVT() <= EVT::i64 &&
+ DstTy.getSimpleVT() >= EVT::i16 &&
"Unknown FP_TO_SINT to lower!");
// These are really Legal.
- if (DstTy == MVT::i32 &&
+ if (DstTy == EVT::i32 &&
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
return std::make_pair(SDValue(), SDValue());
if (Subtarget->is64Bit() &&
- DstTy == MVT::i64 &&
+ DstTy == EVT::i64 &&
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
return std::make_pair(SDValue(), SDValue());
@@ -5066,18 +5066,18 @@
unsigned Opc;
switch (DstTy.getSimpleVT()) {
default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
- case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
- case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
- case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
+ case EVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
+ case EVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
+ case EVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
}
SDValue Chain = DAG.getEntryNode();
SDValue Value = Op.getOperand(0);
if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
- assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
+ assert(DstTy == EVT::i64 && "Invalid FP_TO_SINT to lower!");
Chain = DAG.getStore(Chain, dl, Value, StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0);
- SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
+ SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), EVT::Other);
SDValue Ops[] = {
Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
};
@@ -5089,15 +5089,15 @@
// Build the FP_TO_INT*_IN_MEM
SDValue Ops[] = { Chain, Value, StackSlot };
- SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
+ SDValue FIST = DAG.getNode(Opc, dl, EVT::Other, Ops, 3);
return std::make_pair(FIST, StackSlot);
}
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType().isVector()) {
- if (Op.getValueType() == MVT::v2i32 &&
- Op.getOperand(0).getValueType() == MVT::v2f64) {
+ if (Op.getValueType() == EVT::v2i32 &&
+ Op.getOperand(0).getValueType() == EVT::v2f64) {
return Op;
}
return SDValue();
@@ -5126,12 +5126,12 @@
SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
LLVMContext *Context = DAG.getContext();
DebugLoc dl = Op.getDebugLoc();
- MVT VT = Op.getValueType();
- MVT EltVT = VT;
+ EVT VT = Op.getValueType();
+ EVT EltVT = VT;
if (VT.isVector())
EltVT = VT.getVectorElementType();
std::vector<Constant*> CV;
- if (EltVT == MVT::f64) {
+ if (EltVT == EVT::f64) {
Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
CV.push_back(C);
CV.push_back(C);
@@ -5153,15 +5153,15 @@
SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
LLVMContext *Context = DAG.getContext();
DebugLoc dl = Op.getDebugLoc();
- MVT VT = Op.getValueType();
- MVT EltVT = VT;
+ EVT VT = Op.getValueType();
+ EVT EltVT = VT;
unsigned EltNum = 1;
if (VT.isVector()) {
EltVT = VT.getVectorElementType();
EltNum = VT.getVectorNumElements();
}
std::vector<Constant*> CV;
- if (EltVT == MVT::f64) {
+ if (EltVT == EVT::f64) {
Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
CV.push_back(C);
CV.push_back(C);
@@ -5179,10 +5179,10 @@
false, 16);
if (VT.isVector()) {
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getNode(ISD::XOR, dl, MVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
+ DAG.getNode(ISD::XOR, dl, EVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64,
Op.getOperand(0)),
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, Mask)));
} else {
return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
}
@@ -5193,8 +5193,8 @@
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
- MVT VT = Op.getValueType();
- MVT SrcVT = Op1.getValueType();
+ EVT VT = Op.getValueType();
+ EVT SrcVT = Op1.getValueType();
// If second operand is smaller, extend it first.
if (SrcVT.bitsLT(VT)) {
@@ -5212,7 +5212,7 @@
// First get the sign bit of second operand.
std::vector<Constant*> CV;
- if (SrcVT == MVT::f64) {
+ if (SrcVT == EVT::f64) {
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
} else {
@@ -5230,18 +5230,18 @@
// Shift sign bit right or left if the two operands have different types.
if (SrcVT.bitsGT(VT)) {
- // Op0 is MVT::f32, Op1 is MVT::f64.
- SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
- SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
- DAG.getConstant(32, MVT::i32));
- SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
- SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
+ // Op0 is EVT::f32, Op1 is EVT::f64.
+ SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2f64, SignBit);
+ SignBit = DAG.getNode(X86ISD::FSRL, dl, EVT::v2f64, SignBit,
+ DAG.getConstant(32, EVT::i32));
+ SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4f32, SignBit);
+ SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f32, SignBit,
DAG.getIntPtrConstant(0));
}
// Clear first operand sign bit.
CV.clear();
- if (VT == MVT::f64) {
+ if (VT == EVT::f64) {
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
} else {
@@ -5342,7 +5342,7 @@
break;
}
if (Opcode != 0) {
- SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::i32);
SmallVector<SDValue, 4> Ops;
for (unsigned i = 0; i != NumOperands; ++i)
Ops.push_back(Op.getOperand(i));
@@ -5353,7 +5353,7 @@
}
// Otherwise just emit a CMP with 0, which is the TEST pattern.
- return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
+ return DAG.getNode(X86ISD::CMP, dl, EVT::i32, Op,
DAG.getConstant(0, Op.getValueType()));
}
@@ -5366,11 +5366,11 @@
return EmitTest(Op0, X86CC, DAG);
DebugLoc dl = Op0.getDebugLoc();
- return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
+ return DAG.getNode(X86ISD::CMP, dl, EVT::i32, Op0, Op1);
}
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
- assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
+ assert(Op.getValueType() == EVT::i8 && "SetCC type must be 8-bit integer");
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
@@ -5413,18 +5413,18 @@
// instruction. Since the shift amount is in-range-or-undefined, we know
// that doing a bittest on the i16 value is ok. We extend to i32 because
// the encoding for the i16 version is larger than the i32 version.
- if (LHS.getValueType() == MVT::i8)
- LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
+ if (LHS.getValueType() == EVT::i8)
+ LHS = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, LHS);
// If the operand types disagree, extend the shift amount to match. Since
// BT ignores high bits (like shifts) we can use anyextend.
if (LHS.getValueType() != RHS.getValueType())
RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
- SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
+ SDValue BT = DAG.getNode(X86ISD::BT, dl, EVT::i32, LHS, RHS);
unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
- return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
- DAG.getConstant(Cond, MVT::i8), BT);
+ return DAG.getNode(X86ISD::SETCC, dl, EVT::i8,
+ DAG.getConstant(Cond, EVT::i8), BT);
}
}
@@ -5432,8 +5432,8 @@
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
- return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
- DAG.getConstant(X86CC, MVT::i8), Cond);
+ return DAG.getNode(X86ISD::SETCC, dl, EVT::i8,
+ DAG.getConstant(X86CC, EVT::i8), Cond);
}
SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
@@ -5441,16 +5441,16 @@
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
SDValue CC = Op.getOperand(2);
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
DebugLoc dl = Op.getDebugLoc();
if (isFP) {
unsigned SSECC = 8;
- MVT VT0 = Op0.getValueType();
- assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
- unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
+ EVT VT0 = Op0.getValueType();
+ assert(VT0 == EVT::v4f32 || VT0 == EVT::v2f64);
+ unsigned Opc = VT0 == EVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
bool Swap = false;
switch (SetCCOpcode) {
@@ -5481,20 +5481,20 @@
if (SSECC == 8) {
if (SetCCOpcode == ISD::SETUEQ) {
SDValue UNORD, EQ;
- UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
- EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
+ UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, EVT::i8));
+ EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, EVT::i8));
return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
}
else if (SetCCOpcode == ISD::SETONE) {
SDValue ORD, NEQ;
- ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
- NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
+ ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, EVT::i8));
+ NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, EVT::i8));
return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
}
llvm_unreachable("Illegal FP comparison");
}
// Handle all other FP comparisons here.
- return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
+ return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, EVT::i8));
}
// We are handling one of the integer comparisons here. Since SSE only has
@@ -5505,13 +5505,13 @@
switch (VT.getSimpleVT()) {
default: break;
- case MVT::v8i8:
- case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
- case MVT::v4i16:
- case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
- case MVT::v2i32:
- case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
- case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
+ case EVT::v8i8:
+ case EVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
+ case EVT::v4i16:
+ case EVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
+ case EVT::v2i32:
+ case EVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
+ case EVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
}
switch (SetCCOpcode) {
@@ -5533,7 +5533,7 @@
// Since SSE has no unsigned integer comparisons, we need to flip the sign
// bits of the inputs before performing those operations.
if (FlipSigns) {
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
EltVT);
std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
@@ -5585,7 +5585,7 @@
SDValue Cmp = Cond.getOperand(1);
unsigned Opc = Cmp.getOpcode();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
bool IllegalFPCMov = false;
if (VT.isFloatingPoint() && !VT.isVector() &&
@@ -5600,11 +5600,11 @@
}
if (addTest) {
- CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+ CC = DAG.getConstant(X86::COND_NE, EVT::i8);
Cond = EmitTest(Cond, X86::COND_NE, DAG);
}
- SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
SmallVector<SDValue, 4> Ops;
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
// condition is true.
@@ -5712,7 +5712,7 @@
X86::CondCode CCode =
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
CCode = X86::GetOppositeBranchCondition(CCode);
- CC = DAG.getConstant(CCode, MVT::i8);
+ CC = DAG.getConstant(CCode, EVT::i8);
SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
// Look for an unconditional branch following this conditional branch.
// We need this because we need to reverse the successors in order
@@ -5729,7 +5729,7 @@
X86::CondCode CCode =
(X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
CCode = X86::GetOppositeBranchCondition(CCode);
- CC = DAG.getConstant(CCode, MVT::i8);
+ CC = DAG.getConstant(CCode, EVT::i8);
Cond = Cmp;
addTest = false;
}
@@ -5742,14 +5742,14 @@
X86::CondCode CCode =
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
CCode = X86::GetOppositeBranchCondition(CCode);
- CC = DAG.getConstant(CCode, MVT::i8);
+ CC = DAG.getConstant(CCode, EVT::i8);
Cond = Cond.getOperand(0).getOperand(1);
addTest = false;
}
}
if (addTest) {
- CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+ CC = DAG.getConstant(X86::COND_NE, EVT::i8);
Cond = EmitTest(Cond, X86::COND_NE, DAG);
}
return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
@@ -5776,15 +5776,15 @@
SDValue Flag;
- MVT IntPtr = getPointerTy();
- MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
+ EVT IntPtr = getPointerTy();
+ EVT SPTy = Subtarget->is64Bit() ? EVT::i64 : EVT::i32;
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
Flag = Chain.getValue(1);
- SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
SDValue Ops[] = { Chain,
DAG.getTargetExternalSymbol("_alloca", IntPtr),
DAG.getRegister(X86::EAX, IntPtr),
@@ -5827,7 +5827,7 @@
if (const char *bzeroEntry = V &&
V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
- MVT IntPtr = getPointerTy();
+ EVT IntPtr = getPointerTy();
const Type *IntPtrTy = TD->getIntPtrType();
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
@@ -5849,7 +5849,7 @@
uint64_t SizeVal = ConstantSize->getZExtValue();
SDValue InFlag(0, 0);
- MVT AVT;
+ EVT AVT;
SDValue Count;
ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
unsigned BytesLeft = 0;
@@ -5861,29 +5861,29 @@
// If the value is a constant, then we can potentially use larger sets.
switch (Align & 3) {
case 2: // WORD aligned
- AVT = MVT::i16;
+ AVT = EVT::i16;
ValReg = X86::AX;
Val = (Val << 8) | Val;
break;
case 0: // DWORD aligned
- AVT = MVT::i32;
+ AVT = EVT::i32;
ValReg = X86::EAX;
Val = (Val << 8) | Val;
Val = (Val << 16) | Val;
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
- AVT = MVT::i64;
+ AVT = EVT::i64;
ValReg = X86::RAX;
Val = (Val << 32) | Val;
}
break;
default: // Byte aligned
- AVT = MVT::i8;
+ AVT = EVT::i8;
ValReg = X86::AL;
Count = DAG.getIntPtrConstant(SizeVal);
break;
}
- if (AVT.bitsGT(MVT::i8)) {
+ if (AVT.bitsGT(EVT::i8)) {
unsigned UBytes = AVT.getSizeInBits() / 8;
Count = DAG.getIntPtrConstant(SizeVal / UBytes);
BytesLeft = SizeVal % UBytes;
@@ -5893,7 +5893,7 @@
InFlag);
InFlag = Chain.getValue(1);
} else {
- AVT = MVT::i8;
+ AVT = EVT::i8;
Count = DAG.getIntPtrConstant(SizeVal);
Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
InFlag = Chain.getValue(1);
@@ -5908,7 +5908,7 @@
Dst, InFlag);
InFlag = Chain.getValue(1);
- SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
@@ -5918,24 +5918,24 @@
if (TwoRepStos) {
InFlag = Chain.getValue(1);
Count = Size;
- MVT CVT = Count.getValueType();
+ EVT CVT = Count.getValueType();
SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
- DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
- Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
+ DAG.getConstant((AVT == EVT::i64) ? 7 : 3, CVT));
+ Chain = DAG.getCopyToReg(Chain, dl, (CVT == EVT::i64) ? X86::RCX :
X86::ECX,
Left, InFlag);
InFlag = Chain.getValue(1);
- Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+ Tys = DAG.getVTList(EVT::Other, EVT::Flag);
Ops.clear();
Ops.push_back(Chain);
- Ops.push_back(DAG.getValueType(MVT::i8));
+ Ops.push_back(DAG.getValueType(EVT::i8));
Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
} else if (BytesLeft) {
// Handle the last 1 - 7 bytes.
unsigned Offset = SizeVal - BytesLeft;
- MVT AddrVT = Dst.getValueType();
- MVT SizeVT = Size.getValueType();
+ EVT AddrVT = Dst.getValueType();
+ EVT SizeVT = Size.getValueType();
Chain = DAG.getMemset(Chain, dl,
DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
@@ -5970,9 +5970,9 @@
return SDValue();
// DWORD aligned
- MVT AVT = MVT::i32;
+ EVT AVT = EVT::i32;
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
- AVT = MVT::i64;
+ AVT = EVT::i64;
unsigned UBytes = AVT.getSizeInBits() / 8;
unsigned CountVal = SizeVal / UBytes;
@@ -5993,7 +5993,7 @@
Src, InFlag);
InFlag = Chain.getValue(1);
- SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
@@ -6005,9 +6005,9 @@
if (BytesLeft) {
// Handle the last 1 - 7 bytes.
unsigned Offset = SizeVal - BytesLeft;
- MVT DstVT = Dst.getValueType();
- MVT SrcVT = Src.getValueType();
- MVT SizeVT = Size.getValueType();
+ EVT DstVT = Dst.getValueType();
+ EVT SrcVT = Src.getValueType();
+ EVT SizeVT = Size.getValueType();
Results.push_back(DAG.getMemcpy(Chain, dl,
DAG.getNode(ISD::ADD, dl, DstVT, Dst,
DAG.getConstant(Offset, DstVT)),
@@ -6019,7 +6019,7 @@
SrcSV, SrcSVOff + Offset));
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&Results[0], Results.size());
}
@@ -6043,7 +6043,7 @@
SDValue FIN = Op.getOperand(1);
// Store gp_offset
SDValue Store = DAG.getStore(Op.getOperand(0), dl,
- DAG.getConstant(VarArgsGPOffset, MVT::i32),
+ DAG.getConstant(VarArgsGPOffset, EVT::i32),
FIN, SV, 0);
MemOps.push_back(Store);
@@ -6051,7 +6051,7 @@
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
FIN, DAG.getIntPtrConstant(4));
Store = DAG.getStore(Op.getOperand(0), dl,
- DAG.getConstant(VarArgsFPOffset, MVT::i32),
+ DAG.getConstant(VarArgsFPOffset, EVT::i32),
FIN, SV, 0);
MemOps.push_back(Store);
@@ -6068,7 +6068,7 @@
SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
MemOps.push_back(Store);
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOps[0], MemOps.size());
}
@@ -6198,10 +6198,10 @@
SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);
unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
- SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
- SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
- DAG.getConstant(X86CC, MVT::i8), Cond);
- return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
+ SDValue Cond = DAG.getNode(Opc, dl, EVT::i32, LHS, RHS);
+ SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, EVT::i8,
+ DAG.getConstant(X86CC, EVT::i8), Cond);
+ return DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, SetCC);
}
// ptest intrinsics. The intrinsic these come from are designed to return
// an integer value, not just an instruction so lower it to the ptest
@@ -6228,10 +6228,10 @@
SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);
- SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
- SDValue CC = DAG.getConstant(X86CC, MVT::i8);
- SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
- return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
+ SDValue Test = DAG.getNode(X86ISD::PTEST, dl, EVT::i32, LHS, RHS);
+ SDValue CC = DAG.getConstant(X86CC, EVT::i8);
+ SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, EVT::i8, CC, Test);
+ return DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, SetCC);
}
// Fix vector shift instructions where the last operand is a non-immediate
@@ -6257,7 +6257,7 @@
return SDValue();
unsigned NewIntNo = 0;
- MVT ShAmtVT = MVT::v4i32;
+ EVT ShAmtVT = EVT::v4i32;
switch (IntNo) {
case Intrinsic::x86_sse2_pslli_w:
NewIntNo = Intrinsic::x86_sse2_psll_w;
@@ -6284,7 +6284,7 @@
NewIntNo = Intrinsic::x86_sse2_psra_d;
break;
default: {
- ShAmtVT = MVT::v2i32;
+ ShAmtVT = EVT::v2i32;
switch (IntNo) {
case Intrinsic::x86_mmx_pslli_w:
NewIntNo = Intrinsic::x86_mmx_psll_w;
@@ -6315,11 +6315,11 @@
break;
}
}
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(NewIntNo, MVT::i32),
+ DAG.getConstant(NewIntNo, EVT::i32),
Op.getOperand(1), ShAmt);
}
}
@@ -6333,7 +6333,7 @@
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
SDValue Offset =
DAG.getConstant(TD->getPointerSize(),
- Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
+ Subtarget->is64Bit() ? EVT::i64 : EVT::i32);
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, getPointerTy(),
FrameAddr, Offset),
@@ -6349,7 +6349,7 @@
SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true);
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
@@ -6384,7 +6384,7 @@
MF.getRegInfo().addLiveOut(StoreAddrReg);
return DAG.getNode(X86ISD::EH_RETURN, dl,
- MVT::Other,
+ EVT::Other,
Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
}
@@ -6417,40 +6417,40 @@
// Load the pointer to the nested function into R11.
unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
SDValue Addr = Trmp;
- OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
+ OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16),
Addr, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
- DAG.getConstant(2, MVT::i64));
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
+ DAG.getConstant(2, EVT::i64));
OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
// Load the 'nest' parameter value into R10.
// R10 is specified in X86CallingConv.td
OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
- DAG.getConstant(10, MVT::i64));
- OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
+ DAG.getConstant(10, EVT::i64));
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16),
Addr, TrmpAddr, 10);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
- DAG.getConstant(12, MVT::i64));
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
+ DAG.getConstant(12, EVT::i64));
OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
// Jump to the nested function.
OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
- DAG.getConstant(20, MVT::i64));
- OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
+ DAG.getConstant(20, EVT::i64));
+ OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16),
Addr, TrmpAddr, 20);
unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
- DAG.getConstant(22, MVT::i64));
- OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
+ DAG.getConstant(22, EVT::i64));
+ OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, EVT::i8), Addr,
TrmpAddr, 22);
SDValue Ops[] =
- { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
+ { Trmp, DAG.getNode(ISD::TokenFactor, dl, EVT::Other, OutChains, 6) };
return DAG.getMergeValues(Ops, 2, dl);
} else {
const Function *Func =
@@ -6498,32 +6498,32 @@
SDValue OutChains[4];
SDValue Addr, Disp;
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
- DAG.getConstant(10, MVT::i32));
- Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
+ DAG.getConstant(10, EVT::i32));
+ Disp = DAG.getNode(ISD::SUB, dl, EVT::i32, FPtr, Addr);
const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
OutChains[0] = DAG.getStore(Root, dl,
- DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
+ DAG.getConstant(MOV32ri|N86Reg, EVT::i8),
Trmp, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
- DAG.getConstant(1, MVT::i32));
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
+ DAG.getConstant(1, EVT::i32));
OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
- DAG.getConstant(5, MVT::i32));
- OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
+ DAG.getConstant(5, EVT::i32));
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, EVT::i8), Addr,
TrmpAddr, 5, false, 1);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
- DAG.getConstant(6, MVT::i32));
+ Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
+ DAG.getConstant(6, EVT::i32));
OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
SDValue Ops[] =
- { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
+ { Trmp, DAG.getNode(ISD::TokenFactor, dl, EVT::Other, OutChains, 4) };
return DAG.getMergeValues(Ops, 2, dl);
}
}
@@ -6552,37 +6552,37 @@
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo &TFI = *TM.getFrameInfo();
unsigned StackAlignment = TFI.getStackAlignment();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
// Save FP Control Word to stack slot
int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
+ SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, EVT::Other,
DAG.getEntryNode(), StackSlot);
// Load FP Control Word from stack slot
- SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
+ SDValue CWD = DAG.getLoad(EVT::i16, dl, Chain, StackSlot, NULL, 0);
// Transform as necessary
SDValue CWD1 =
- DAG.getNode(ISD::SRL, dl, MVT::i16,
- DAG.getNode(ISD::AND, dl, MVT::i16,
- CWD, DAG.getConstant(0x800, MVT::i16)),
- DAG.getConstant(11, MVT::i8));
+ DAG.getNode(ISD::SRL, dl, EVT::i16,
+ DAG.getNode(ISD::AND, dl, EVT::i16,
+ CWD, DAG.getConstant(0x800, EVT::i16)),
+ DAG.getConstant(11, EVT::i8));
SDValue CWD2 =
- DAG.getNode(ISD::SRL, dl, MVT::i16,
- DAG.getNode(ISD::AND, dl, MVT::i16,
- CWD, DAG.getConstant(0x400, MVT::i16)),
- DAG.getConstant(9, MVT::i8));
+ DAG.getNode(ISD::SRL, dl, EVT::i16,
+ DAG.getNode(ISD::AND, dl, EVT::i16,
+ CWD, DAG.getConstant(0x400, EVT::i16)),
+ DAG.getConstant(9, EVT::i8));
SDValue RetVal =
- DAG.getNode(ISD::AND, dl, MVT::i16,
- DAG.getNode(ISD::ADD, dl, MVT::i16,
- DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
- DAG.getConstant(1, MVT::i16)),
- DAG.getConstant(3, MVT::i16));
+ DAG.getNode(ISD::AND, dl, EVT::i16,
+ DAG.getNode(ISD::ADD, dl, EVT::i16,
+ DAG.getNode(ISD::OR, dl, EVT::i16, CWD1, CWD2),
+ DAG.getConstant(1, EVT::i16)),
+ DAG.getConstant(3, EVT::i16));
return DAG.getNode((VT.getSizeInBits() < 16 ?
@@ -6590,70 +6590,70 @@
}
SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
- MVT OpVT = VT;
+ EVT VT = Op.getValueType();
+ EVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
- if (VT == MVT::i8) {
+ if (VT == EVT::i8) {
// Zero extend to i32 since there is not an i8 bsr.
- OpVT = MVT::i32;
+ OpVT = EVT::i32;
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
}
// Issue a bsr (scan bits in reverse) which also sets EFLAGS.
- SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
+ SDVTList VTs = DAG.getVTList(OpVT, EVT::i32);
Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
// If src is zero (i.e. bsr sets ZF), returns NumBits.
SmallVector<SDValue, 4> Ops;
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
- Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
+ Ops.push_back(DAG.getConstant(X86::COND_E, EVT::i8));
Ops.push_back(Op.getValue(1));
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
// Finally xor with NumBits-1.
Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
- if (VT == MVT::i8)
- Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
+ if (VT == EVT::i8)
+ Op = DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, Op);
return Op;
}
SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
- MVT OpVT = VT;
+ EVT VT = Op.getValueType();
+ EVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
- if (VT == MVT::i8) {
- OpVT = MVT::i32;
+ if (VT == EVT::i8) {
+ OpVT = EVT::i32;
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
}
// Issue a bsf (scan bits forward) which also sets EFLAGS.
- SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
+ SDVTList VTs = DAG.getVTList(OpVT, EVT::i32);
Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
// If src is zero (i.e. bsf sets ZF), returns NumBits.
SmallVector<SDValue, 4> Ops;
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(NumBits, OpVT));
- Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
+ Ops.push_back(DAG.getConstant(X86::COND_E, EVT::i8));
Ops.push_back(Op.getValue(1));
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
- if (VT == MVT::i8)
- Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
+ if (VT == EVT::i8)
+ Op = DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, Op);
return Op;
}
SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
- assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
+ EVT VT = Op.getValueType();
+ assert(VT == EVT::v2i64 && "Only know how to lower V2I64 multiply");
DebugLoc dl = Op.getDebugLoc();
// ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
@@ -6670,26 +6670,26 @@
SDValue B = Op.getOperand(1);
SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
- A, DAG.getConstant(32, MVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32),
+ A, DAG.getConstant(32, EVT::i32));
SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
- B, DAG.getConstant(32, MVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32),
+ B, DAG.getConstant(32, EVT::i32));
SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32),
A, B);
SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32),
A, Bhi);
SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32),
Ahi, B);
AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
- AloBhi, DAG.getConstant(32, MVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32),
+ AloBhi, DAG.getConstant(32, EVT::i32));
AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
- AhiBlo, DAG.getConstant(32, MVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32),
+ AhiBlo, DAG.getConstant(32, EVT::i32));
SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
return Res;
@@ -6753,29 +6753,29 @@
}
// Also sets EFLAGS.
- SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
+ SDVTList VTs = DAG.getVTList(N->getValueType(0), EVT::i32);
SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
SDValue SetCC =
DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
- DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
+ DAG.getConstant(Cond, EVT::i32), SDValue(Sum.getNode(), 1));
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
return Sum;
}
SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
- MVT T = Op.getValueType();
+ EVT T = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
unsigned Reg = 0;
unsigned size = 0;
switch(T.getSimpleVT()) {
default:
assert(false && "Invalid value type!");
- case MVT::i8: Reg = X86::AL; size = 1; break;
- case MVT::i16: Reg = X86::AX; size = 2; break;
- case MVT::i32: Reg = X86::EAX; size = 4; break;
- case MVT::i64:
+ case EVT::i8: Reg = X86::AL; size = 1; break;
+ case EVT::i16: Reg = X86::AX; size = 2; break;
+ case EVT::i32: Reg = X86::EAX; size = 4; break;
+ case EVT::i64:
assert(Subtarget->is64Bit() && "Node not type legal!");
Reg = X86::RAX; size = 8;
break;
@@ -6785,9 +6785,9 @@
SDValue Ops[] = { cpIn.getValue(0),
Op.getOperand(1),
Op.getOperand(3),
- DAG.getTargetConstant(size, MVT::i8),
+ DAG.getTargetConstant(size, EVT::i8),
cpIn.getValue(1) };
- SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
SDValue cpOut =
DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
@@ -6797,17 +6797,17 @@
SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
SelectionDAG &DAG) {
assert(Subtarget->is64Bit() && "Result not type legalized?");
- SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
SDValue TheChain = Op.getOperand(0);
DebugLoc dl = Op.getDebugLoc();
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
- SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
- SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
+ SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, EVT::i64, rd.getValue(1));
+ SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, EVT::i64,
rax.getValue(2));
- SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
- DAG.getConstant(32, MVT::i8));
+ SDValue Tmp = DAG.getNode(ISD::SHL, dl, EVT::i64, rdx,
+ DAG.getConstant(32, EVT::i8));
SDValue Ops[] = {
- DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
+ DAG.getNode(ISD::OR, dl, EVT::i64, rax, Tmp),
rdx.getValue(1)
};
return DAG.getMergeValues(Ops, 2, dl);
@@ -6816,7 +6816,7 @@
SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc();
- MVT T = Node->getValueType(0);
+ EVT T = Node->getValueType(0);
SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
DAG.getConstant(0, T), Node->getOperand(2));
return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
@@ -6886,24 +6886,24 @@
void X86TargetLowering::
ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG, unsigned NewOp) {
- MVT T = Node->getValueType(0);
+ EVT T = Node->getValueType(0);
DebugLoc dl = Node->getDebugLoc();
- assert (T == MVT::i64 && "Only know how to expand i64 atomics");
+ assert (T == EVT::i64 && "Only know how to expand i64 atomics");
SDValue Chain = Node->getOperand(0);
SDValue In1 = Node->getOperand(1);
- SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
Node->getOperand(2), DAG.getIntPtrConstant(0));
- SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
Node->getOperand(2), DAG.getIntPtrConstant(1));
// This is a generalized SDNode, not an AtomicSDNode, so it doesn't
// have a MemOperand. Pass the info through as a normal operand.
SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
- SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
+ SDVTList Tys = DAG.getVTList(EVT::i32, EVT::i32, EVT::Other);
SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, OpsF, 2));
Results.push_back(Result.getValue(2));
}
@@ -6922,42 +6922,42 @@
FP_TO_INTHelper(SDValue(N, 0), DAG, true);
SDValue FIST = Vals.first, StackSlot = Vals.second;
if (FIST.getNode() != 0) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// Return a load from the stack slot.
Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
}
return;
}
case ISD::READCYCLECOUNTER: {
- SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
SDValue TheChain = N->getOperand(0);
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
- SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
+ SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, EVT::i32,
rd.getValue(1));
- SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
+ SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, EVT::i32,
eax.getValue(2));
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
SDValue Ops[] = { eax, edx };
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Ops, 2));
Results.push_back(edx.getValue(1));
return;
}
case ISD::ATOMIC_CMP_SWAP: {
- MVT T = N->getValueType(0);
- assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
+ EVT T = N->getValueType(0);
+ assert (T == EVT::i64 && "Only know how to expand i64 Cmp and Swap");
SDValue cpInL, cpInH;
- cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
- DAG.getConstant(0, MVT::i32));
- cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
- DAG.getConstant(1, MVT::i32));
+ cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(2),
+ DAG.getConstant(0, EVT::i32));
+ cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(2),
+ DAG.getConstant(1, EVT::i32));
cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
cpInL.getValue(1));
SDValue swapInL, swapInH;
- swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
- DAG.getConstant(0, MVT::i32));
- swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
- DAG.getConstant(1, MVT::i32));
+ swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(3),
+ DAG.getConstant(0, EVT::i32));
+ swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(3),
+ DAG.getConstant(1, EVT::i32));
swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
cpInH.getValue(1));
swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
@@ -6965,14 +6965,14 @@
SDValue Ops[] = { swapInH.getValue(0),
N->getOperand(1),
swapInH.getValue(1) };
- SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
- MVT::i32, Result.getValue(1));
+ EVT::i32, Result.getValue(1));
SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
- MVT::i32, cpOutL.getValue(2));
+ EVT::i32, cpOutL.getValue(2));
SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, OpsF, 2));
Results.push_back(cpOutH.getValue(1));
return;
}
@@ -7144,7 +7144,7 @@
return Subtarget->is64Bit() || NumBits1 < 64;
}
-bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
+bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
if (!VT1.isInteger() || !VT2.isInteger())
return false;
unsigned NumBits1 = VT1.getSizeInBits();
@@ -7159,14 +7159,14 @@
return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
}
-bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
+bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
// x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
- return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
+ return VT1 == EVT::i32 && VT2 == EVT::i64 && Subtarget->is64Bit();
}
-bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const {
+bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
// i16 instructions are longer (0x66 prefix) and potentially slower.
- return !(VT1 == MVT::i32 && VT2 == MVT::i16);
+ return !(VT1 == EVT::i32 && VT2 == EVT::i16);
}
/// isShuffleMaskLegal - Targets can use this to indicate that they only
@@ -7175,7 +7175,7 @@
/// are assumed to be legal.
bool
X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
- MVT VT) const {
+ EVT VT) const {
// Only do shuffles on 128-bit vector types for now.
if (VT.getSizeInBits() == 64)
return false;
@@ -7196,7 +7196,7 @@
bool
X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
- MVT VT) const {
+ EVT VT) const {
unsigned NumElts = VT.getVectorNumElements();
// FIXME: This collection of masks seems suspect.
if (NumElts == 2)
@@ -7941,7 +7941,7 @@
}
static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
- MVT EVT, LoadSDNode *&LDBase,
+ EVT EVT, LoadSDNode *&LDBase,
unsigned &LastLoadedElt,
SelectionDAG &DAG, MachineFrameInfo *MFI,
const TargetLowering &TLI) {
@@ -7985,8 +7985,8 @@
static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI) {
DebugLoc dl = N->getDebugLoc();
- MVT VT = N->getValueType(0);
- MVT EVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EVT = VT.getVectorElementType();
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
unsigned NumElems = VT.getVectorNumElements();
@@ -8010,7 +8010,7 @@
LD->getSrcValue(), LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
} else if (NumElems == 4 && LastLoadedElt == 1) {
- SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
+ SDVTList Tys = DAG.getVTList(EVT::v2i64, EVT::Other);
SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
@@ -8029,7 +8029,7 @@
// If we have SSE[12] support, try to form min/max nodes.
if (Subtarget->hasSSE2() &&
- (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
+ (LHS.getValueType() == EVT::f32 || LHS.getValueType() == EVT::f64) &&
Cond.getOpcode() == ISD::SETCC) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
@@ -8117,7 +8117,7 @@
unsigned ShAmt = TrueC->getAPIntValue().logBase2();
return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
- DAG.getConstant(ShAmt, MVT::i8));
+ DAG.getConstant(ShAmt, EVT::i8));
}
// Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
@@ -8135,9 +8135,9 @@
// Optimize cases that will turn into an LEA instruction. This requires
// an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
- if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
+ if (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i64) {
uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
- if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
+ if (N->getValueType(0) == EVT::i32) Diff = (unsigned)Diff;
bool isFastMultiplier = false;
if (Diff < 10) {
@@ -8210,15 +8210,15 @@
// shift amount.
if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
SDValue Cond = N->getOperand(3);
- Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
- DAG.getConstant(CC, MVT::i8), Cond);
+ Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8,
+ DAG.getConstant(CC, EVT::i8), Cond);
// Zero extend the condition if needed.
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
unsigned ShAmt = TrueC->getAPIntValue().logBase2();
Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
- DAG.getConstant(ShAmt, MVT::i8));
+ DAG.getConstant(ShAmt, EVT::i8));
if (N->getNumValues() == 2) // Dead flag value?
return DCI.CombineTo(N, Cond, SDValue());
return Cond;
@@ -8228,8 +8228,8 @@
// for any integer data type, including i8/i16.
if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
SDValue Cond = N->getOperand(3);
- Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
- DAG.getConstant(CC, MVT::i8), Cond);
+ Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8,
+ DAG.getConstant(CC, EVT::i8), Cond);
// Zero extend the condition if needed.
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
@@ -8244,9 +8244,9 @@
// Optimize cases that will turn into an LEA instruction. This requires
// an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
- if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
+ if (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i64) {
uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
- if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
+ if (N->getValueType(0) == EVT::i32) Diff = (unsigned)Diff;
bool isFastMultiplier = false;
if (Diff < 10) {
@@ -8267,8 +8267,8 @@
if (isFastMultiplier) {
APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
SDValue Cond = N->getOperand(3);
- Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
- DAG.getConstant(CC, MVT::i8), Cond);
+ Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8,
+ DAG.getConstant(CC, EVT::i8), Cond);
// Zero extend the condition if needed.
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
Cond);
@@ -8304,8 +8304,8 @@
if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
return SDValue();
- MVT VT = N->getValueType(0);
- if (VT != MVT::i64)
+ EVT VT = N->getValueType(0);
+ if (VT != EVT::i64)
return SDValue();
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
@@ -8341,14 +8341,14 @@
SDValue NewMul;
if (isPowerOf2_64(MulAmt1))
NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
- DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
+ DAG.getConstant(Log2_64(MulAmt1), EVT::i8));
else
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
DAG.getConstant(MulAmt1, VT));
if (isPowerOf2_64(MulAmt2))
NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
- DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
+ DAG.getConstant(Log2_64(MulAmt2), EVT::i8));
else
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
DAG.getConstant(MulAmt2, VT));
@@ -8371,12 +8371,12 @@
if (!Subtarget->hasSSE2())
return SDValue();
- MVT VT = N->getValueType(0);
- if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
+ EVT VT = N->getValueType(0);
+ if (VT != EVT::v2i64 && VT != EVT::v4i32 && VT != EVT::v8i16)
return SDValue();
SDValue ShAmtOp = N->getOperand(1);
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
DebugLoc DL = N->getDebugLoc();
SDValue BaseShAmt;
if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
@@ -8402,10 +8402,10 @@
} else
return SDValue();
- if (EltVT.bitsGT(MVT::i32))
- BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
- else if (EltVT.bitsLT(MVT::i32))
- BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
+ if (EltVT.bitsGT(EVT::i32))
+ BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, EVT::i32, BaseShAmt);
+ else if (EltVT.bitsLT(EVT::i32))
+ BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, EVT::i32, BaseShAmt);
// The shift amount is identical so we can do a vector shift.
SDValue ValOp = N->getOperand(0);
@@ -8414,41 +8414,41 @@
llvm_unreachable("Unknown shift opcode!");
break;
case ISD::SHL:
- if (VT == MVT::v2i64)
+ if (VT == EVT::v2i64)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32),
ValOp, BaseShAmt);
- if (VT == MVT::v4i32)
+ if (VT == EVT::v4i32)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_d, EVT::i32),
ValOp, BaseShAmt);
- if (VT == MVT::v8i16)
+ if (VT == EVT::v8i16)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, EVT::i32),
ValOp, BaseShAmt);
break;
case ISD::SRA:
- if (VT == MVT::v4i32)
+ if (VT == EVT::v4i32)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrai_d, EVT::i32),
ValOp, BaseShAmt);
- if (VT == MVT::v8i16)
+ if (VT == EVT::v8i16)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrai_w, EVT::i32),
ValOp, BaseShAmt);
break;
case ISD::SRL:
- if (VT == MVT::v2i64)
+ if (VT == EVT::v2i64)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32),
ValOp, BaseShAmt);
- if (VT == MVT::v4i32)
+ if (VT == EVT::v4i32)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_d, EVT::i32),
ValOp, BaseShAmt);
- if (VT == MVT::v8i16)
+ if (VT == EVT::v8i16)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_w, EVT::i32),
ValOp, BaseShAmt);
break;
}
@@ -8465,7 +8465,7 @@
// Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
StoreSDNode *St = cast<StoreSDNode>(N);
- MVT VT = St->getValue().getValueType();
+ EVT VT = St->getValue().getValueType();
if (VT.getSizeInBits() != 64)
return SDValue();
@@ -8474,7 +8474,7 @@
bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
&& Subtarget->hasSSE2();
if ((VT.isVector() ||
- (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
+ (VT == EVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
isa<LoadSDNode>(St->getValue()) &&
!cast<LoadSDNode>(St->getValue())->isVolatile() &&
St->getChain().hasOneUse() && !St->isVolatile()) {
@@ -8514,7 +8514,7 @@
// Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
// pair instead.
if (Subtarget->is64Bit() || F64IsLegal) {
- MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
+ EVT LdVT = Subtarget->is64Bit() ? EVT::i64 : EVT::f64;
SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
Ld->getBasePtr(), Ld->getSrcValue(),
Ld->getSrcValueOffset(), Ld->isVolatile(),
@@ -8522,7 +8522,7 @@
SDValue NewChain = NewLd.getValue(1);
if (TokenFactorIndex != -1) {
Ops.push_back(NewChain);
- NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, LdDL, EVT::Other, &Ops[0],
Ops.size());
}
return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
@@ -8532,13 +8532,13 @@
// Otherwise, lower to two pairs of 32-bit loads / stores.
SDValue LoAddr = Ld->getBasePtr();
- SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
- DAG.getConstant(4, MVT::i32));
+ SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, EVT::i32, LoAddr,
+ DAG.getConstant(4, EVT::i32));
- SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
+ SDValue LoLd = DAG.getLoad(EVT::i32, LdDL, Ld->getChain(), LoAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset(),
Ld->isVolatile(), Ld->getAlignment());
- SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
+ SDValue HiLd = DAG.getLoad(EVT::i32, LdDL, Ld->getChain(), HiAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
Ld->isVolatile(),
MinAlign(Ld->getAlignment(), 4));
@@ -8547,13 +8547,13 @@
if (TokenFactorIndex != -1) {
Ops.push_back(LoLd);
Ops.push_back(HiLd);
- NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, LdDL, EVT::Other, &Ops[0],
Ops.size());
}
LoAddr = St->getBasePtr();
- HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
- DAG.getConstant(4, MVT::i32));
+ HiAddr = DAG.getNode(ISD::ADD, StDL, EVT::i32, LoAddr,
+ DAG.getConstant(4, EVT::i32));
SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
St->getSrcValue(), St->getSrcValueOffset(),
@@ -8563,7 +8563,7 @@
St->getSrcValueOffset() + 4,
St->isVolatile(),
MinAlign(St->getAlignment(), 4));
- return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
+ return DAG.getNode(ISD::TokenFactor, StDL, EVT::Other, LoSt, HiSt);
}
return SDValue();
}
@@ -8618,7 +8618,7 @@
SDValue Op = N->getOperand(0);
if (Op.getOpcode() == ISD::BIT_CONVERT)
Op = Op.getOperand(0);
- MVT VT = N->getValueType(0), OpVT = Op.getValueType();
+ EVT VT = N->getValueType(0), OpVT = Op.getValueType();
if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
VT.getVectorElementType().getSizeInBits() ==
OpVT.getVectorElementType().getSizeInBits()) {
@@ -8833,7 +8833,7 @@
/// with another that has more specific requirements based on the type of the
/// corresponding operand.
const char *X86TargetLowering::
-LowerXConstraint(MVT ConstraintVT) const {
+LowerXConstraint(EVT ConstraintVT) const {
// FP X constraints get lowered to SSE1/2 registers if available, otherwise
// 'f' like normal targets.
if (ConstraintVT.isFloatingPoint()) {
@@ -8895,7 +8895,7 @@
const ConstantInt *CI = C->getConstantIntValue();
if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
// Widen to 64 bits here to get it sign extended.
- Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
+ Result = DAG.getTargetConstant(C->getSExtValue(), EVT::i64);
break;
}
// FIXME gcc accepts some relocatable values here too, but only in certain
@@ -8920,7 +8920,7 @@
// Literal immediates are always ok.
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
// Widen to 64 bits here to get it sign extended.
- Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
+ Result = DAG.getTargetConstant(CST->getSExtValue(), EVT::i64);
break;
}
@@ -8978,33 +8978,33 @@
std::vector<unsigned> X86TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
if (Constraint.size() == 1) {
// FIXME: not handling fp-stack yet!
switch (Constraint[0]) { // GCC X86 Constraint Letters
default: break; // Unknown constraint letter
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget->is64Bit()) {
- if (VT == MVT::i32)
+ if (VT == EVT::i32)
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
X86::ESI, X86::EDI, X86::R8D, X86::R9D,
X86::R10D,X86::R11D,X86::R12D,
X86::R13D,X86::R14D,X86::R15D,
X86::EBP, X86::ESP, 0);
- else if (VT == MVT::i16)
+ else if (VT == EVT::i16)
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
X86::SI, X86::DI, X86::R8W,X86::R9W,
X86::R10W,X86::R11W,X86::R12W,
X86::R13W,X86::R14W,X86::R15W,
X86::BP, X86::SP, 0);
- else if (VT == MVT::i8)
+ else if (VT == EVT::i8)
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
X86::SIL, X86::DIL, X86::R8B,X86::R9B,
X86::R10B,X86::R11B,X86::R12B,
X86::R13B,X86::R14B,X86::R15B,
X86::BPL, X86::SPL, 0);
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
X86::RSI, X86::RDI, X86::R8, X86::R9,
X86::R10, X86::R11, X86::R12,
@@ -9015,13 +9015,13 @@
}
// 32-bit fallthrough
case 'Q': // Q_REGS
- if (VT == MVT::i32)
+ if (VT == EVT::i32)
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
- else if (VT == MVT::i16)
+ else if (VT == EVT::i16)
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
- else if (VT == MVT::i8)
+ else if (VT == EVT::i8)
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
break;
}
@@ -9032,7 +9032,7 @@
std::pair<unsigned, const TargetRegisterClass*>
X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
// First, see if this is a constraint that directly corresponds to an LLVM
// register class.
if (Constraint.size() == 1) {
@@ -9042,19 +9042,19 @@
case 'r': // GENERAL_REGS
case 'R': // LEGACY_REGS
case 'l': // INDEX_REGS
- if (VT == MVT::i8)
+ if (VT == EVT::i8)
return std::make_pair(0U, X86::GR8RegisterClass);
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
return std::make_pair(0U, X86::GR16RegisterClass);
- if (VT == MVT::i32 || !Subtarget->is64Bit())
+ if (VT == EVT::i32 || !Subtarget->is64Bit())
return std::make_pair(0U, X86::GR32RegisterClass);
return std::make_pair(0U, X86::GR64RegisterClass);
case 'f': // FP Stack registers.
// If SSE is enabled for this VT, use f80 to ensure the isel moves the
// value to the correct fpstack register class.
- if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
+ if (VT == EVT::f32 && !isScalarFPTypeInSSEReg(VT))
return std::make_pair(0U, X86::RFP32RegisterClass);
- if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
+ if (VT == EVT::f64 && !isScalarFPTypeInSSEReg(VT))
return std::make_pair(0U, X86::RFP64RegisterClass);
return std::make_pair(0U, X86::RFP80RegisterClass);
case 'y': // MMX_REGS if MMX allowed.
@@ -9069,19 +9069,19 @@
switch (VT.getSimpleVT()) {
default: break;
// Scalar SSE types.
- case MVT::f32:
- case MVT::i32:
+ case EVT::f32:
+ case EVT::i32:
return std::make_pair(0U, X86::FR32RegisterClass);
- case MVT::f64:
- case MVT::i64:
+ case EVT::f64:
+ case EVT::i64:
return std::make_pair(0U, X86::FR64RegisterClass);
// Vector types.
- case MVT::v16i8:
- case MVT::v8i16:
- case MVT::v4i32:
- case MVT::v2i64:
- case MVT::v4f32:
- case MVT::v2f64:
+ case EVT::v16i8:
+ case EVT::v8i16:
+ case EVT::v4i32:
+ case EVT::v2i64:
+ case EVT::v4f32:
+ case EVT::v2f64:
return std::make_pair(0U, X86::VR128RegisterClass);
}
break;
@@ -9119,7 +9119,7 @@
// really want an 8-bit or 32-bit register, map to the appropriate register
// class and return the appropriate register.
if (Res.second == X86::GR16RegisterClass) {
- if (VT == MVT::i8) {
+ if (VT == EVT::i8) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;
@@ -9132,7 +9132,7 @@
Res.first = DestReg;
Res.second = X86::GR8RegisterClass;
}
- } else if (VT == MVT::i32) {
+ } else if (VT == EVT::i32) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;
@@ -9149,7 +9149,7 @@
Res.first = DestReg;
Res.second = X86::GR32RegisterClass;
}
- } else if (VT == MVT::i64) {
+ } else if (VT == EVT::i64) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;
@@ -9174,9 +9174,9 @@
// wrong class. This can happen with constraints like {xmm0} where the
// target independent register mapper will just pick the first match it can
// find, ignoring the required type.
- if (VT == MVT::f32)
+ if (VT == EVT::f32)
Res.second = X86::FR32RegisterClass;
- else if (VT == MVT::f64)
+ else if (VT == EVT::f64)
Res.second = X86::FR64RegisterClass;
else if (X86::VR128RegisterClass->hasType(VT))
Res.second = X86::VR128RegisterClass;
@@ -9191,11 +9191,11 @@
/// getWidenVectorType: given a vector type, returns the type to widen
/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
-/// If there is no vector type that we want to widen to, returns MVT::Other
+/// If there is no vector type that we want to widen to, returns EVT::Other
/// When and where to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
-MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
+EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
assert(VT.isVector());
if (isTypeLegal(VT))
return VT;
@@ -9204,21 +9204,21 @@
// type based on element type. This would speed up our search (though
// it may not be worth it since the size of the list is relatively
// small).
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
// On X86, it make sense to widen any vector wider than 1
if (NElts <= 1)
- return MVT::Other;
+ return EVT::Other;
- for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
- nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
- MVT SVT = (MVT::SimpleValueType)nVT;
+ for (unsigned nVT = EVT::FIRST_VECTOR_VALUETYPE;
+ nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) {
+ EVT SVT = (EVT::SimpleValueType)nVT;
if (isTypeLegal(SVT) &&
SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts)
return SVT;
}
- return MVT::Other;
+ return EVT::Other;
}
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 459b7be..d9c745b 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -382,10 +382,10 @@
/// getOptimalMemOpType - Returns the target specific optimal type for load
/// and store operations as a result of memset, memcpy, and memmove
- /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
+ /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
/// determining it.
virtual
- MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
+ EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr,
SelectionDAG &DAG) const;
@@ -411,7 +411,7 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const;
+ virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
@@ -434,9 +434,9 @@
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
- virtual const char *LowerXConstraint(MVT ConstraintVT) const;
+ virtual const char *LowerXConstraint(EVT ConstraintVT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
@@ -454,7 +454,7 @@
/// error, this returns a register number of 0.
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
@@ -464,7 +464,7 @@
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
/// register EAX to i16 by referencing its sub-register AX.
virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
- virtual bool isTruncateFree(MVT VT1, MVT VT2) const;
+ virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
/// isZExtFree - Return true if any actual instruction that defines a
/// value of type Ty1 implicit zero-extends the value to Ty2 in the result
@@ -475,35 +475,35 @@
/// all instructions that define 32-bit values implicit zero-extend the
/// result out to 64 bits.
virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
- virtual bool isZExtFree(MVT VT1, MVT VT2) const;
+ virtual bool isZExtFree(EVT VT1, EVT VT2) const;
/// isNarrowingProfitable - Return true if it's profitable to narrow
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
/// from i32 to i8 but not from i32 to i16.
- virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const;
+ virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
/// values are assumed to be legal.
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
- MVT VT) const;
+ EVT VT) const;
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
/// used by Targets can use this to indicate if there is a suitable
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
- MVT VT) const;
+ EVT VT) const;
/// ShouldShrinkFPConstant - If true, then instruction selection should
/// seek to shrink the FP constant of the specified type to a smaller type
/// in order to save space and / or reduce runtime.
- virtual bool ShouldShrinkFPConstant(MVT VT) const {
+ virtual bool ShouldShrinkFPConstant(EVT VT) const {
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
// expensive than a straight movsd. On the other hand, it's important to
// shrink long double fp constant since fldt is very slow.
- return !X86ScalarSSEf64 || VT == MVT::f80;
+ return !X86ScalarSSEf64 || VT == EVT::f80;
}
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
@@ -522,17 +522,17 @@
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
- bool isScalarFPTypeInSSEReg(MVT VT) const {
- return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
- (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
+ bool isScalarFPTypeInSSEReg(EVT VT) const {
+ return (VT == EVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
+ (VT == EVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
/// getWidenVectorType: given a vector type, returns the type to widen
/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
- /// If there is no vector type that we want to widen to, returns MVT::Other
+ /// If there is no vector type that we want to widen to, returns EVT::Other
/// When and were to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
- virtual MVT getWidenVectorType(MVT VT) const;
+ virtual EVT getWidenVectorType(EVT VT) const;
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
@@ -610,7 +610,7 @@
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
- SDValue BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, SDValue StackSlot,
+ SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
SelectionDAG &DAG);
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG);
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index b59f8e8..79bd0af 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -2525,24 +2525,24 @@
SDNode *Load = 0;
const MachineFunction &MF = DAG.getMachineFunction();
if (FoldedLoad) {
- MVT VT = *RC->vt_begin();
+ EVT VT = *RC->vt_begin();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
- VT, MVT::Other, &AddrOps[0], AddrOps.size());
+ VT, EVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
}
// Emit the data processing instruction.
- std::vector<MVT> VTs;
+ std::vector<EVT> VTs;
const TargetRegisterClass *DstRC = 0;
if (TID.getNumDefs() > 0) {
DstRC = TID.OpInfo[0].getRegClass(&RI);
VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
+ EVT VT = N->getValueType(i);
+ if (VT != EVT::Other && i >= (unsigned)TID.getNumDefs())
VTs.push_back(VT);
}
if (Load)
@@ -2561,7 +2561,7 @@
RI.needsStackRealignment(MF);
SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
isAligned, TM),
- dl, MVT::Other,
+ dl, EVT::Other,
&AddrOps[0], AddrOps.size());
NewNodes.push_back(Store);
}
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index cae6290..09457a1 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -1262,10 +1262,10 @@
}
namespace llvm {
-unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
+unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
switch (VT.getSimpleVT()) {
default: return Reg;
- case MVT::i8:
+ case EVT::i8:
if (High) {
switch (Reg) {
default: return 0;
@@ -1315,7 +1315,7 @@
return X86::R15B;
}
}
- case MVT::i16:
+ case EVT::i16:
switch (Reg) {
default: return Reg;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
@@ -1351,7 +1351,7 @@
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
return X86::R15W;
}
- case MVT::i32:
+ case EVT::i32:
switch (Reg) {
default: return Reg;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
@@ -1387,7 +1387,7 @@
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
return X86::R15D;
}
- case MVT::i64:
+ case EVT::i64:
switch (Reg) {
default: return Reg;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index f6c119d..c89a57c 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -163,8 +163,8 @@
// getX86SubSuperRegister - X86 utility function. It returns the sub or super
// register of a specific X86 register.
-// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
-unsigned getX86SubSuperRegister(unsigned, MVT, bool High=false);
+// e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX
+unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false);
} // End llvm namespace