diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp
index 1816586..387cebf 100644
--- a/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -468,7 +468,7 @@
   }
 
   while (ShiftAmount--)
-    Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
+    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
                          dl, VT, Victim);
 
   return Victim;
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index de1b2ad..39c08e4 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -624,12 +624,12 @@
                       (implicit SRW)]>;
 
 def SAR8r1c  : Pseudo<(outs GR8:$dst), (ins GR8:$src),
-                      "clrc\n"
+                      "clrc\n\t"
                       "rrc.b\t$dst",
                       [(set GR8:$dst, (MSP430rrc GR8:$src)),
                        (implicit SRW)]>;
 def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
-                      "clrc\n"
+                      "clrc\n\t"
                       "rrc.w\t$dst",
                       [(set GR16:$dst, (MSP430rrc GR16:$src)),
                        (implicit SRW)]>;
diff --git a/test/CodeGen/MSP430/2009-05-17-Shift.ll b/test/CodeGen/MSP430/2009-05-17-Shift.ll
new file mode 100644
index 0000000..b048bb3
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-05-17-Shift.ll
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -march=msp430 | grep rra | count 1
+
+define i16 @lsr2u16(i16 %x.arg) nounwind {
+        %retval = alloca i16
+        %x = alloca i16
+        store i16 %x.arg, i16* %x
+        %1 = load i16* %x
+        %2 = lshr i16 %1, 2
+        store i16 %2, i16* %retval
+        br label %return
+return:
+        %3 = load i16* %retval
+        ret i16 %3
+
+}
\ No newline at end of file