Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
8-byte align doubles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index b957fe6..0b945ab 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -187,9 +187,9 @@
if (MO.isRegister()) {
rv = enumRegToMachineReg(MO.getReg());
- // Special encoding for MTCRF and MFCRF, which uses a bit mask for the
+ // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
// register, not the register number directly.
- if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFCRF) &&
+ if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
rv = 0x80 >> rv;
}