Make some implicit conversions explicit, to avoid compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56927 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3d0a2d6..4e8c47c 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2927,7 +2927,7 @@
// Expand memcpy to a series of load and store ops if the size operand falls
// below a certain threshold.
std::vector<MVT> MemOps;
- uint64_t Limit = -1;
+ uint64_t Limit = uint64_t(-1);
if (!AlwaysInline)
Limit = TLI.getMaxStoresPerMemcpy();
unsigned DstAlign = Align; // Destination alignment can change.
@@ -2985,7 +2985,7 @@
// Expand memmove to a series of load and store ops if the size operand falls
// below a certain threshold.
std::vector<MVT> MemOps;
- uint64_t Limit = -1;
+ uint64_t Limit = uint64_t(-1);
if (!AlwaysInline)
Limit = TLI.getMaxStoresPerMemmove();
unsigned DstAlign = Align; // Destination alignment can change.
diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp
index 6c7b68b..5d765a4 100644
--- a/lib/VMCore/AsmWriter.cpp
+++ b/lib/VMCore/AsmWriter.cpp
@@ -385,7 +385,7 @@
// Find the type plane in the module map
ValueMap::iterator MI = mMap.find(V);
- return MI == mMap.end() ? -1 : MI->second;
+ return MI == mMap.end() ? -1 : (int)MI->second;
}
@@ -397,7 +397,7 @@
initialize();
ValueMap::iterator FI = fMap.find(V);
- return FI == fMap.end() ? -1 : FI->second;
+ return FI == fMap.end() ? -1 : (int)FI->second;
}