commit aec5861bb6ace3734163c000cb75ca2e22e29caa
author Nadav Rotem <nadav.rotem@intel.com> Tue Sep 13 19:17:42 2011 +0000
committer Nadav Rotem <nadav.rotem@intel.com> Tue Sep 13 19:17:42 2011 +0000
tree b554e33aa701259868dc31f14a20761fc497514c
parent 48ae99fac4010e6bbe5550fd914cc879091049fb

Add vselect target support for targets that do not support blend but do support
xor/and/or (For example SSE2).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 71399ce..171400a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6440,6 +6440,10 @@
       Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
                                 &Operands[0], Operands.size()));
       break;
+    case ISD::VSELECT:
+      Scalars.push_back(getNode(ISD::SELECT, dl, EltVT,
+                                &Operands[0], Operands.size()));
+      break;
     case ISD::SHL:
     case ISD::SRA:
     case ISD::SRL: