commit af02d599bddfe945ab551f5a934ec0d7ecab3c0b
author Andrew Lenharth <alenhar2@cs.uiuc.edu> Sat Jun 14 05:48:15 2008 +0000
committer Andrew Lenharth <alenhar2@cs.uiuc.edu> Sat Jun 14 05:48:15 2008 +0000
tree 53d5d29cee43a7eb314904ce4ada56e735f3efea
parent 8fa21137b2ce4345e0fa8d58978e1bd83a4530b9

add missing atomic intrinsic from gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index dd5a350..87bb1db 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1254,6 +1254,7 @@
   case ISD::ATOMIC_LOAD_AND:
   case ISD::ATOMIC_LOAD_OR:
   case ISD::ATOMIC_LOAD_XOR:
+  case ISD::ATOMIC_LOAD_NAND:
   case ISD::ATOMIC_LOAD_MIN:
   case ISD::ATOMIC_LOAD_MAX:
   case ISD::ATOMIC_LOAD_UMIN:
@@ -4285,6 +4286,7 @@
   case ISD::ATOMIC_LOAD_AND:
   case ISD::ATOMIC_LOAD_OR:
   case ISD::ATOMIC_LOAD_XOR:
+  case ISD::ATOMIC_LOAD_NAND:
   case ISD::ATOMIC_LOAD_MIN:
   case ISD::ATOMIC_LOAD_MAX:
   case ISD::ATOMIC_LOAD_UMIN: