Make the -verify-regalloc command line option available to base classes as
RegAllocBase::VerifyEnabled.
Run the machine code verifier in a few interesting places during RegAllocGreedy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122107 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index d8c1b3d..8dbb568 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -328,6 +328,9 @@
SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit)
.splitAroundLoop(Loop->getLoop());
+ if (VerifyEnabled)
+ MF->verify(this);
+
// We have new split regs, don't assign anything.
return 0;
}
@@ -400,6 +403,9 @@
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
+ if (VerifyEnabled)
+ MF->verify(this);
+
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
DomTree = &getAnalysis<MachineDominatorTree>();
ReservedRegs = TRI->getReservedRegs(*MF);