EXTRACT_VECTOR_ELEMENT can have result type different from element type.
Remove the assertion and generalize the code for ARM NEON stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80498 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 12d7b2e..0484fd0 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -2691,13 +2691,20 @@
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- assert((VT == MVT::i8 || VT == MVT::i16) &&
- "unexpected type for custom-lowering vector extract");
SDValue Vec = Op.getOperand(0);
SDValue Lane = Op.getOperand(1);
+
+ // FIXME: This is invalid for 8 and 16-bit elements - the information about
+ // sign / zero extension is lost!
Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
- return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
+
+ if (VT.bitsLT(MVT::i32))
+ Op = DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
+ else if (VT.bitsGT(MVT::i32))
+ Op = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op);
+
+ return Op;
}
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {