diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index eb433aa..7d18a86 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2498,8 +2498,7 @@
   if (DAG.MaskedValueIsZero(SDValue(N, 0),
                             APInt::getAllOnesValue(VT.getSizeInBits())))
     return DAG.getConstant(0, VT);
-  // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c))
-  // iff (trunc c) == c
+  // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
   if (N1.getOpcode() == ISD::TRUNCATE &&
       N1.getOperand(0).getOpcode() == ISD::AND &&
       N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
@@ -2507,8 +2506,8 @@
     if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
       MVT TruncVT = N1.getValueType();
       SDValue N100 = N1.getOperand(0).getOperand(0);
-      uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
-                        N101C->getZExtValue();
+      APInt TruncC = N101C->getAPIntValue();
+      TruncC.trunc(TruncVT.getSizeInBits());
       return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
                          DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
                                      DAG.getNode(ISD::TRUNCATE,
@@ -2632,8 +2631,7 @@
     }
   }
   
-  // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c))
-  // iff (trunc c) == c
+  // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
   if (N1.getOpcode() == ISD::TRUNCATE &&
       N1.getOperand(0).getOpcode() == ISD::AND &&
       N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
@@ -2641,8 +2639,8 @@
     if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
       MVT TruncVT = N1.getValueType();
       SDValue N100 = N1.getOperand(0).getOperand(0);
-      uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
-                        N101C->getZExtValue();
+      APInt TruncC = N101C->getAPIntValue();
+      TruncC.trunc(TruncVT.getSizeInBits());
       return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
                          DAG.getNode(ISD::AND, N->getDebugLoc(),
                                      TruncVT,
@@ -2757,8 +2755,7 @@
     }
   }
 
-  // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
-  // iff (trunc c) == c
+  // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
   if (N1.getOpcode() == ISD::TRUNCATE &&
       N1.getOperand(0).getOpcode() == ISD::AND &&
       N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
@@ -2766,8 +2763,8 @@
     if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
       MVT TruncVT = N1.getValueType();
       SDValue N100 = N1.getOperand(0).getOperand(0);
-      uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
-                        N101C->getZExtValue();
+      APInt TruncC = N101C->getAPIntValue();
+      TruncC.trunc(TruncVT.getSizeInBits());
       return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
                          DAG.getNode(ISD::AND, N->getDebugLoc(),
                                      TruncVT,
@@ -4359,8 +4356,8 @@
     SDValue Int = N0.getOperand(0);
     MVT IntVT = Int.getValueType();
     if (IntVT.isInteger() && !IntVT.isVector()) {
-      Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 
-                        DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
+      Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
+              DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
       AddToWorkList(Int.getNode());
       return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
                          N->getValueType(0), Int);
@@ -4395,7 +4392,7 @@
     MVT IntVT = Int.getValueType();
     if (IntVT.isInteger() && !IntVT.isVector()) {
       Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 
-                        DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
+             DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
       AddToWorkList(Int.getNode());
       return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
                          N->getValueType(0), Int);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4dd5dd2..0b3d979 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3110,9 +3110,9 @@
                              DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
                                          Tmp2, DAG.getIntPtrConstant(i)),
                              CC);
-        Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
-                             DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
-                             DAG.getConstant(0, EltVT));
+        Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i], DAG.getConstant(
+                                  APInt::getAllOnesValue(EltVT.getSizeInBits()),
+                                  EltVT), DAG.getConstant(0, EltVT));
       }
       Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
       break;
@@ -6291,7 +6291,9 @@
     unsigned len = VT.getSizeInBits();
     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
       //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
-      SDValue Tmp2 = DAG.getConstant(VT.getIntegerVTBitMask() & mask[i], VT);
+      unsigned EltSize = VT.isVector() ?
+        VT.getVectorElementType().getSizeInBits() : len;
+      SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
       SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
       Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
                        DAG.getNode(ISD::AND, VT,
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1b0d61c..d8f895d 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -845,12 +845,13 @@
   SDValue NegOne;
   if (VT.isVector()) {
     MVT EltVT = VT.getVectorElementType();
-    SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
+    SDValue NegOneElt =
+      getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT);
     std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
     NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT,
                      &NegOnes[0], NegOnes.size());
   } else {
-    NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
+    NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
   }
 
   return getNode(ISD::XOR, DL, VT, Val, NegOne);
@@ -2772,7 +2773,7 @@
       return N1;
     case ISD::OR:
       if (!VT.isVector())
-        return getConstant(VT.getIntegerVTBitMask(), VT);
+        return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
       // For vectors, we can't easily build an all one vector, just return
       // the LHS.
       return N1;